M16C User Manual.pdf

Address Match InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERAddress Match InterruptAn address match interrupt is generated when the address match interrupt address register contents matchthe program counter value. Two address match interrupts can be set, each of which can be enabled anddisabled by an address match interrupt enable bit. Address match interrupts are not affected by the interruptenable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)for an address match interrupt varies depending on the instruction being executed. Note that when usingthe external data bus in width of 8 bits, the address match interrupt cannot be used for external area.Figure 1.14.12 shows the address match interrupt-related registers.Address match interrupt enable registerb7 b6 b5 b4 b3 b2 b1 b0Symbol Address When resetAIER 000916 XXXXXX002Bit symbolBit nameFunctionR WAIER0Address match interrupt 0 0 : Interrupt disabledenable bit 1 : Interrupt enabledAIER1 Address match interrupt 1enable bit0 : Interrupt disabled1 : Interrupt enabledNothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turns out tobe indeterminated.Address match interrupt register i (i = 0, 1)(b23)b7(b19)b3(b16)(b15)b0 b7(b8)b0 b7b0Symbol Address When resetRMAD0 001216 to 001016 X0000016RMAD1 001616 to 001416 X0000016FunctionAddress setting register for address match interruptValues that can be set R W0000016 toFFFFF16Nothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turns out tobe indeterminated.Figure 1.14.12. Address match interrupt-related registers68