M16C User Manual.pdf

DMACMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDMACThis microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent tomemory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given ahigher right of using the bus than the CPU, which leads to working the cycle stealing method. On thisaccount, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.16.1 shows the block diagramof the DMAC. Table 1.16.1 shows the DMAC specifications. Figures 1.16.2 to 1.16.4 show the registersused by the DMAC.Address bus DMA0 source pointer SAR0(20)(addresses002216 to 002016)DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 forward address pointer (20) (Note)DMA0 transfer counter reload register TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 002916, 002816)(addresses 003216 to 003016) DMA0 transfer counter TCR0 (16)DMA1 destination pointer DAR1 (20) (addresses 003616 to 003416)DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note) (addresses 003916, 003816) DMA1 transfer counter TCR1 (16)DMA latch high-order bits DMA latch low-order bits Data bus low-order bitsData bus high-order bitsNote: Pointer is incremented by a DMA request.Figure 1.16.1. Block diagram of DMACEither a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transferrequest signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by theinterrupt priority level. The DMA transfer doesn't affect any interrupts either.If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer requestsignal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMAtransfer cycle, there can be instances in which the number of transfer requests doesn't agree with thenumber of transfers. For details, see the description of the DMA request bit.73