M16C User Manual.pdf

Clock asynchronous serial I/O (UART) modeMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(2) Clock asynchronous serial I/O (UART) modeThe UART mode allows transmitting and receiving data after setting the desired transfer rate and transferdata format. Tables 1.19.5 and 1.19.6 list the specifications of the UART mode. Figure 1.19.15 showsthe UARTi transmit/receive mode register.Table 1.19.5. Specifications of UART Mode (1)ItemSpecificationTransfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected• Start bit: 1 bit• Parity bit: Odd, even, or nothing as selected• Stop bit: 1 bit or 2 bits as selectedTransfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :fi/16(n+1) (Note 1) fi = f1, f8, f32• When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)_______ _______ _______ _______Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalidTransmission start condition • To start transmission, the following requirements must be met:- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”______________- When CTS function selected, CTS input level = “L”Reception start condition • To start reception, the following requirements must be met:- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”- Start bit detectionInterrupt request • When transmittinggeneration timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 ataddress 037D16) = “0”: Interrupts requested when data transfer from UARTitransfer buffer register to UARTi transmit register is completed- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 ataddress 037D16) = “1”: Interrupts requested when data transmission fromUARTi transfer register is completed• When receiving- Interrupts requested when data transfer from UARTi receive register toUARTi receive buffer register is completedError detection • Overrun error (Note 3)This error occurs when the next data is ready before contents of UARTireceive buffer register are read out• Framing errorThis error occurs when the number of stop bits set is not detected• Parity errorThis error occurs when if parity is enabled, the number of 1’s in parity andcharacter bits does not match the number of 1’s set• Error sum flagThis flag is set (= 1) when any of the overrun, framing, and parity errors isencounteredNote 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.Note 2: fEXT is input from the CLKi pin.Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also thatthe UARTi receive interrupt request bit is not set to “1”.129