M16C User Manual.pdf

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER4.1.3 Hardware InterruptsHardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.(1) Special interruptsSpecial interrupts are non-maskable interrupts.• Reset____________Reset occurs if an “L” is input to the RESET pin._______• NMI interrupt______________An NMI interrupt occurs if an “L” is input to the NMI pin.________• DBC interruptThis interrupt is exclusively for the debugger, do not use it in other circumstances.• Watchdog timer interruptGenerated by the watchdog timer.• Single-step interruptThis interrupt is exclusively for the debugger, do not use it in other circumstances. With the debugflag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.• Address match interruptAn address match interrupt occurs immediately before the instruction held in the address indicated bythe address match interrupt register is executed with the address match interrupt enable bit set to “1”.If an address other than the first address of the instruction in the address match interrupt register is set,no address match interrupt occurs. For address match interrupt, see 2.11 Address match Interrupt.(2) Peripheral I/O interruptsA peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functionsare dependent on classes of products, so the interrupt factors too are dependent on classes ofproducts. The interrupt vector table is the same as the one for software interrupt numbers 0 through31 the INI instruction uses. Peripheral I/O interrupts are maskable interrupts.• Bus collision detection interruptThis is an interrupt that the serial I/O bus collision detection generates.• DMA0 interrupt, DMA1 interruptThese are interrupts DMA generates.• Key-input interrupt___A key-input interrupt occurs if an “L” is input to the KI pin.• A-D conversion interruptThis is an interrupt that the A-D converter generates.• UART0, UART1 and UART2 transmission interruptThese are interrupts that the serial I/O transmission generates.• UART0, UART1 and UART2 reception interruptThese are interrupts that the serial I/O reception generates.• Timer A0 interrupt through timer A4 interruptThese are interrupts that timer A generates• Timer B0 interrupt through timer B2 interruptThese are interrupts that timer B generates.________________• INT0 interrupt through INT2 interrupt____________An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.488