M16C User Manual.pdf

DMACMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER2.9 DMAC2.9.1 OverviewDMAC transfers one data item held in the source address to the destination address every time a transferrequest is generated. The following is a DMAC overview.(1) Source address and destination addressBoth the register which indicates a source and the register which indicates a destination comprise of24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, theaddress in either the source register or the destination register can be incremented. However, bothregisters cannot be incremented. The links between the source and destination are as follows:(a) A fixed address from an arbitrary 1M bytes space(b) An arbitrary 1M bytes space from a fixed address(c) A fixed address from another fixed address(2) The number of bits of data transferredThe number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is selected,up to 128 K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can betransferred. The transfer counter is decremented each time one bit of data is transferred, and a DMAinterrupt request occurs when the transfer counter underflows.(3) DMA transfer factor________The DMA transfer factor can be selected from the following 25 factors: falling edge/two edges of INT0/________INT1 pin, timer A0 interrupt request through timer A4 interrupt request, timer B0 interrupt requestthrough timer B5 interrupt request, UART0 transmission interrupt request, UART0 reception interruptrequest, UART1 transmission/UART1 reception interrupt request, UART2 transmission interrupt request,UART2 reception interrupt request, SI/O 3, 4 interrupt request, A-D conversion interrupt request,and software trigger.When software trigger is selected, DMA transfer is generated by writing “1” to software DMA interruptrequest bit. When other factor is selected, DMA transfer is generated by generating correspondinginterrupt request.(4) Channel priorityIf DMA0 transfer request and DMA1 transfer request occur simultaneously, priority is given to DMA0.(5) Writing to a registerWhen writing to the source register or the destination register with DMA enabled, the content of theregister with a fixed address will change at the time of writing. Therefore, the user should not write toa register with a fixed address when the DMA enable bit is set to “1”. The contents of the register with‘forward direction’ selected, and the transfer counter, are changed when reloaded. A reload occurseither when the transfer counter underflows, or when the DMA enable bit is re-enabled, after havingbeen disabled.The reload register can be written to, as in normal conditions.(6) Reading to a registerThe reload register can be read to, as in normal conditions.416