M16C User Manual.pdf

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bitsof the interrupt control register. When an interrupt request occurs, the interrupt priority level is comparedwith the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.Therefore, setting the interrupt priority level to “0” disables the interrupt.Table 4.2.1 shows the settings of interrupt priority levels and Table 4.2.2 shows the interrupt levels enabled,according to the consist of the IPL.The following are conditions under which an interrupt is accepted:· interrupt enable flag (I flag) = 1· interrupt request bit = 1· interrupt priority level > IPLThe interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL areindependent, and they are not affected by one another.Table 4.2.1. Settings of interrupt priority levelsTable 4.2.2. Interrupt levels enabled accordingto the contents of the IPLInterrupt prioritylevel select bitInterrupt prioritylevelPriorityorderIPLEnabled interrupt priority levelsb2 b1 b0IPL2 IPL1 IPL00 0 0Level 0 (interrupt disabled)0 0 0Interrupt levels 1 and above are enabled0 0 1Level 1Low0 0 1Interrupt levels 2 and above are enabled0 1 0Level 20 1 0Interrupt levels 3 and above are enabled0 1 1Level 30 1 1Interrupt levels 4 and above are enabled1 0 0Level 41 0 0Interrupt levels 5 and above are enabled1 0 1Level 51 0 1Interrupt levels 6 and above are enabled1 1 0Level 61 1 0Interrupt levels 7 and above are enabled1 1 1Level 7High1 1 1All maskable interrupts are disabledWhen either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt inthe following timing:• When changing the IPL using the REIT instruction, the reflection takes effect as of the instructionthat is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takeseffect as of the instruction that is executed in 3 cycles after the last clock cycle involved in theinstruction used.• When changing the interrupt priority level using the MOV or similar instruction, the reflection takeseffect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved inthe instruction used.494