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GE_OEC_9600_C-Arms

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16 C-Arm Control<br />

TECHNIQUE PROCESSOR PCB<br />

Assy. #00-876737 - Sch. #00-876735<br />

Assy. #00-877744 - Sch. #00-877742<br />

OVERVIEW<br />

The Technique Processor PCB (see Figures 12 and 13) is responsible for<br />

initializing and controlling the <strong>9600</strong> C-Arm. Application software for the system<br />

resides on the SRAM card located in the on-board solid state disk drive U13.<br />

The Technique Processor PCB plugs into the Motherboard which serves as the<br />

backplane of the card rack (see Figures 1, 9, and 10). The Analog Interface PCB<br />

is a slave to the Technique Processor, carrying out commands received on the<br />

PC bus.<br />

Two versions of this PCB exist and either of these boards may be used in a<br />

system. The difference between the two PCBs, is the communication circuitry<br />

which is discussed in System Communications in this section.<br />

RESET CIRCUITRY AND WATCHDOG TIMER<br />

When power is applied to the Technique Processor, power-on reset circuitry<br />

(U34 & U9) cause the 80C188 microprocessor (U30) to be reset. An external<br />

reset pulse on pin 57 is also generated. This external reset pulse (RST and<br />

*RST via U10) is sent to the real-time clock U29, Dual-Port RAM control PAL<br />

U4, the Control Panel Processor PCB, and to the PIOs located on the Analog<br />

Interface PCB which sets these items to a default state. Switch S2 is used to<br />

manually reset the Technique Processor.<br />

U34 also serves as a “Watchdog Timer” for microprocessor U30. Pin 30 (PCS4)<br />

from the microcprocessor must reset U34 at pin 1 every 1.2 seconds or else U34<br />

will reset the microprocessor via U9 as described above. The purpose of the<br />

“Watchdog” is to interrupt the microprocessor from any unwanted software loops<br />

that may occur.<br />

CPU & BUS INTERFACE<br />

Once reset, microprocessor U30 retrieves instructions from the Boot EPROM<br />

U14 used to initialize the Technique Processor. This is accomplished via the<br />

internal bus interface circuitry composed of address and I/O decoding circuits<br />

U44 - U47 and signal buffer U36. The bus interface circuitry also enables the<br />

Technique Processor to interface with other on-board devices such as SRAM<br />

(U16 - U19), EEPROM (U20), and a serial communications controller U39.

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