GE_OEC_9600_C-Arms

Image System 33
Column Filter Circuitry
The column filter section of the PCB is comprised of U1, U2, U3, SW1, SW2 and the
interconnecting components. The purpose of this circuitry is to produce a signal that
cancels column artifacts of the CCD sensor. The CCD sensor manufacturer tests each
sensor IC and provides data that locates column artifacts that appear in the video image.
This data is stored in EPROM U1. The data is read by U2, an address controller EPLD
(Erasable Programmable Logic Device) which performs the logic, counter, multiplexing
and positioning functions with the data it receives. One byte of data from the EPROM
contains information for two pixels. The EPLD transmits four bits of correction data (DA
0-3) per pixel at a time to the D/A converter U3. The cancellation is done at the pixel
clock rate for the EIA (60 Hz) camera at 21.5 MHz. The pixel clock and HDRV
(horizontal drive) are the only control lines required by U2.
SW1 provides 1/2 pixel adjustment of error correction data by changing the phase of the
clock of the output register of U2 and the D/A. SW2 adjusts the horizontal position of the
entire video image. The D/A converts the data to an analog signal to be added to the
video and input to the Pixel Filter circuit. Potentiometer R1 is used to fine tune the
amplitude of the analog signal. See the Image System Calibration section of this
manual for details of adjustments to this circuitry.
Camera gain is used as the reference voltage for the D/A converter. As different
technique is used by the generator, the gain of the camera is changed. In order to better
cancel the column artifact at both high and low gain, the camera gain signal controls the
D/A to allow the canceling signal to match and track in amplitude.
Power to the Column Filter portion (+5) comes from a remote three terminal regulator
(U20) on the Image Function PCB. It enters the Pixel/Column Filter PCB at J3 pin 2.
R12
C11
J1
J2
PIXEL & COL. FLTR
C16
C12
R17
R13
Q1
R2
R15
C2 U3
R10
U4
R9
C10
R1
R16
C4
C15
C6
R11
+
R3
R4
L1
C5
C3
R14
C1 L3TP1
J3 L2
R8
VID
TP2
GND
R18
R5
C13
CR1
U2
RP1
+
R7
C9
R6
C8
SW1
C7 C14
U1 SW2
00-878047- ( )
Figure 19 - Pixel/Column Filter PCB