Actas JP2011 - Universidad de La Laguna

Actas XXII Jornadas de Paralelismo (JP2011) , La Laguna, Tenerife, 7-9 septiembre 2011Normalized execution time1.31.21.11.00.90.80.70.60.50.40.30.20.10.0BarnesFlushingFlushing DC:2CholeskyFlushing DC:4Flushing DC:81.60 2.42FFTOceanRadiosityRaytrace-optVolrendWater-NsqTomcatvUnstructuredFaceRecMPGdecMPGencSpeechRecBlackscholesCannealSwaptionsFluidanimatex264ApacheSPEC-JBBAverageFig. 11. Execution time normalized to the base system. DC:2, DC:4, and DC:8 stand for directory caches with their sizedivided by 2, 4, and 8, respectively.Dynamic energy2.01.81.61.41.21.00.80.60.40.20.01. Base 2. Updating 3. Flushing 4. Flushing DC:2 5. Flushing DC:4 6. Flushing DC:8BarnesCholeskyDirectoryCache MemoryController NetworkFFTOceanRadiosityRaytrace-optVolrendWater-NsqTomcatvUnstructuredFaceRecMPGdecMPGencSpeechRecBlackscholesCannealSwaptionsFluidanimatex264ApacheSPEC-JBBAverageFig. 12. Dynamic energy consumption normalized to the base system. DC:2, DC:4, and DC:8 stand for directory caches withtheir size divided by 2, 4, and 8, respectively.3.02The static energy consumption is not shown in Figure12 because it is really tight to application runtime.Besides, in directory caches, it also dependson the directory size. Thus, when using directorycaches 2, 4, and 8 times smaller than that in the basesystem, the static power consumption is reduced by48%, 74%, and 86%, respectively.VI. ConclusionsThe proposal made in this paper aims to improvethe effectiveness of directory caches. It takes advantageof the fact that most referred memory blocksare private and, therefore, they do not require coherencemaintenance. Thus, directory caches do notkeep track of them. Since the amount of informationstored by directory caches is drastically reduced, thenumber of blocks invalidated from processor cachesdue to replacements in directory caches also lowers(by about 57% on average). This contributes to increasesystem performance (15%) or to reduce thestorage requirements of directory caches (8 times).Due to the simplicity of the proposed technique,it can be implemented without modifying the coherenceprotocol or the processor hardware, being itsimplementation feasible in actual systems.AcknowledgmentsThis work has been supported by Generalitat Valencianaunder Grant PROMETEO/2008/060.Referencias[1] P. Conway et al., “Cache hierarchy and memory subsystemof the AMD opteron processor,” IEEE Micro, vol.30, no. 2, pp. 16–29, Apr. 2010.[2] B. W. O’Krafka et al., “An empirical evaluation of twomemory-efficient directory methods,” in 17th Int’l Symp.on Computer Architecture (ISCA), June 1990, pp. 138–147.[3] A. Gupta et al., “Reducing memory traffic requirementsfor scalable directory-based cache coherence schemes,”in Int’l Conference on Parallel Processing (ICPP), Aug.1990, pp. 312–321.[4] N. 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