Actas JP2011 - Universidad de La Laguna

Actas XXII Jornadas de Paralelismo (JP2011) , La Laguna, Tenerife, 7-9 septiembre 2011Efficient hardware support for locksynchronization in Many-core CMPsJosé L. Abellán, Juan Fernández y Manuel E. Acacio 1Abstract—Synchronization is of paramount importance to exploitthread-level parallelism on many-core CMPs.In these architectures, synchronization mechanismsusually rely on shared variables to coordinate multithreadedaccess to shared data structures thus avoidingdata dependency conflicts. Lock synchronizationis known to be a key limitation to performance andscalability. On the one hand, lock acquisition throughbusy waiting on shared variables generates additionalcoherence activity which interferes with applications.On the other hand, lock contention causes serializationwhich results in performance degradation. Thispaper proposes and evaluates GLocks, a hardwaresupportedimplementation for highly-contended locksin the context of many-core CMPs. GLocks use atoken-based message-passing protocol over a dedicatednetwork built on state-of-the-art technology.This approach skips the memory hierarchy to providea non-intrusive, extremely efficient and fair lockimplementation with negligible impact on energy consumptionor die area. A comprehensive comparisonagainst the most efficient shared-memory-based lockimplementation for a set of microbenchmarks and realapplications quantifies the goodness of GLocks. Performanceresults show an average reduction of 42%and 14% in execution time, an average reduction of76% and 23% in network traffic, and also an averagereduction of 78% and 28% in energy-delay 2 product(ED 2 P) metric for the full CMP for the microbenchmarksand the real applications, respectively. In lightof our performance results, we can conclude thatGLocks satisfy our initial working hypothesis. GLocksminimize cache-coherence network traffic due to locksynchronization which translates into reduced powerconsumption and execution time.Keywords— Many-core CMP, lock synchronization,global line.I. Introduction and MotivationWHILE the number of cores currently offeredin general-purpose CMPs has already goneabove ten (e.g., the 12-core 2-die AMD’s Magny-Cours design [1]), the well-known Moore’s Law statesthat soon there will be available on-chip the resourcesrequired to integrate dozens of cores or even hundredsof them. CMPs of this kind are commonlyreferred to as many-core CMPs. For instance, the experimentalresearch microprocessor: 48-core SinglechipCloud Computer [2].If current trends continue, future many-coreCMP architectures will implement the hardwaremanaged,implicitly-addressed, coherent cachesmemory model [3]. With this memory model, allon-chip storage is used for private and shared cachesthat are kept coherent by hardware. Communicationbetween threads is performed by writing to andreading from shared memory. In order to guarantee1 Departamento de Ingeniería y Tecnología deComputadores, Universidad de Murcia, e-mail:{jl.abellan,juanf,meacacio}@ditec.um.esFig. 1. Potential benefits for Raytrace when using ideal locks.the integrity of shared data structures, most currentsystems support synchronization through a combinationof hardware (such as atomic read-modify-writeinstructions like test&set) and software (higher-levelmechanisms such as locks or barriers implementedatop the underlying hardware primitives) [4]. In thisway, implementations of locks usually rely on sharedvariables which are atomically updated.The use of shared variables for lock synchronizationhas two important implications for performanceand scalability in many-core CMPs. First, the cachecoherence protocol must come into play in order tomaintain the consistency of shared variables acrossall levels of the memory hierarchy. Coherence activitytranslates into traffic injection in the interconnectionnetwork. As a result, an ever-growingamount of resources may need to be devoted to supportlock synchronization as the number of coresin many-core CMPs increases. Moreover, lock acquisitionand release operations timing is deeply affectedby the performance and scalability of the cachecoherence protocol especially under the presence ofhighly-contended locks. Second, lock contention haslong been recognized as a key impediment to performanceand scalability since it causes serialization [5].Consequently, the longer the idle time spent on lockacquisition and release operations, the larger the parallelefficiency reduction.As an evidence, we show in Figure 1 the potentialbenefits to performance when lock synchronizationsdo not involve the cache coherence protocol andhave zero latency. To do that, the Raytrace applicationfrom the SPLASH-2 benchmark suite [6] isrun by using distinct lock implementations (for detailsabout the evaluation see Section III). In eachcase, we highlight in gray the fraction of the executiontime due to the locks. Shared-memory-basedlocks use test-and-test&set (see TATAS bar inFigure 1). In turn, ideal locks (see IDEAL bar in Figure1) do not deal with the cache coherence protocolto eliminate any inherited performance or scalabilityside effect. Besides, lock acquisition and releaseJP2011-209