Actas JP2011 - Universidad de La Laguna

Actas XXII Jornadas de Paralelismo (JP2011) , La Laguna, Tenerife, 7-9 septiembre 2011Tableless Distributed Routing inHeterogeneous MPSoC SystemsJosé Cano 1 , José Flich 1 , José Duato 1 , Marcello Coppola 2 , Riccardo Locatelli 2Abstract—In application-specific SoCs, the irregularity of thetopology ends up in a complex implementation of therouting algorithm, usually relying on routing tablesimplemented with memory structures. As system sizeincreases, the routing table increases in size with nonnegligibleimpact on power, area and latency overheads.In this paper we propose a routing mechanismfor application-specific SoCs able to implement in anefficient manner (without requiring routing tables andusing a small logic block in every switch) a routing algorithmin those irregular networks. The mechanismrelies on a tool that maps the initial irregular topologyof the SoC system into a logical regular structurewhere the mechanism itself can be applied. We providedetails of both the mapping tool and the routingmechanism. Evaluation results show the effectivenessof the mapping tool as well as the low area and timingrequirements of the mechanism.Keywords—Systems-on-Chip, Networks-on-Chip, Routing.I. IntroductionAs technology advances, systems-on-chip (SoC)designs become more complex with the inclusion ofmany IP components. Tens (and in the near futureseveral hundreds) of elements need to be connectedwithin the same chip, thus requiring an efficient onchipinterconnect. Usually, the system design is customizedtaking into account the future applicationthat will be running on top of it. Traffic patternsare known in advance, and the interconnect is customizedtoo. The net result of such design approachis a network within the chip [1] [2] with no regularshape and with varying switch complexities and linkbandwidths. Figure 1 shows an example where IPblocks are connected by using an on-chip networkwith 28 switches. As can be observed, the networktopology is totally irregular and heterogeneous.Two key pillars of an interconnect are the topologyand the routing algorithm. The topology sets thephysical connection pattern between end nodes and,as indicated previously, in application-specific SoCsystems is usually irregular. The routing algorithm,on the other hand, sets the paths that messages needto take within the network. Once the topology is set,then, the routing algorithm needs to be applied andmessages need to be instructed about the paths tofollow. In order to implement the routing algorithmtwo trends can be followed: source routing and distributedrouting [3].1 Grupo de Arquitecturas Paralelas , Universitat Politècnicade València. E-mail: jocare@gap.upv.es, {jflich,jduato}@disca.upv.esSTMicroelectronics , Grenoble, France. E-mail:{marcello.coppola, riccardo.locatelli}@st.comFig. 1. Example of a complex irregular topology for anapplication-specific SoC system. P means producers andC means consumers.Today, the majority of application-specific SoCsystems in current products are using irregulartopologies based on well-known on-chip technologies(examples are Spidergon STNoC [4], Arteris NoC [5],Sonics MicroNetwork [6] and AMBA [7]). Those irregularsolutions are mainly based on source routingand address decoding, and normally need a compleximplementation of the routing algorithm (with routingtables using memory structures). Indeed, thelack of regularity in the topology prevents simplificationsin the routing algorithm design. As systemsize increases, the routing table increases in sizewith non-negligible impact on power, area and latencyoverheads (for a comparison between logicbasedrouting and tables, refer to [8]).In this paper we address the implementation ofthe routing algorithm in application-specific SoC systemswhere the topology is set by the application,thus being totally irregular. The aim is to design amechanism (LBDRx) that enables the use of tablelessdistributed routing on every switch with a constantand reduced logic cost, regardless of systemsize. We also provide a tool able to map the initialirregular topology into a logical regular structurewhere the LBDRx approach can be used. By doingthis, the routing algorithm can be efficiently implementedin the SoC design with no need of routingtables and with no topology change.There has been considerable work on routing algorithmsfor irregular NoCs [9] [10] [11]. However,none of the solutions allow the implementation of distributedrouting algorithms in irregular NoCs topologieswith no routing tables and minimum logic.The rest of the paper is organized as follows. SectionII describes the concrete contribution of the paperin a preliminary subsection, in order to clarifyJP2011-675