Actas JP2011 - Universidad de La Laguna

Actas XXII Jornadas de Paralelismo (JP2011) , La Laguna, Tenerife, 7-9 septiembre 2011B. Compute the Connection PatternThe connection pattern considers only links connectingswitches (switch-to-switch links) and the directionof each link (unidirectional links are considered).Several restrictions are enforced in this step(considering LBDR2):1. Any switch has at maximum 12 outgoing portsand 12 incoming ports, possibly having lessnumber of ports, and not necessarily the samenumber of input and output ports.2. In every switch one possible direction out of 12can be taken through a single output port. Thedirections are the ones supported by LBDR2 (2-hop and 1-hop links depicted in Figure 3).Taking into account the previous restrictions,mappings with link lengths longer than the targetedLBDRx version will become not valid. Figure 7(a)shows the connectivity pattern for the previous twomapping cases. As can be seen, the second mappingcase is not compatible with LBDR2 since it containsa 3-hop link. Notice however, that if we use LBDR3both mappings are, then, supported.Fig. 7. Example of (a) connectivity pattern applied to twodifferent mappings, and (b) mapped topology with therouting algorithm applied.C. Compute a Proper Routing AlgorithmOnce we have obtained a correct mapping we needto check whether the mapped topology contains cyclesor not. In order to avoid them, it will be necessaryto apply a routing algorithm. In our case, therouting algorithm used is the Segment-Based Routing(SR) [13], a technique that divides the networkinto segments and puts a routing restriction in eachsegment. A routing restriction is placed between twoconsecutive links and prevents any message from usingboth links sequentially. Drawing routing restrictionsis a way of representing a routing algorithmsince restrictions establish the allowed paths. In orderto compute the routing restrictions, only 1-hoplinks in the mapped topology are assumed. As commentedabove, this assumption simplifies the LBDRxlogic and still allows to reach our objective of avoidingcycles.In the first mapping in Figure 7(a), a cycle can beformed between switches 0, 3, and 2 in the counterclockwise direction. Figure 7(b) shows the validmapped topology with the unidirectional routing restrictionapplied at switch 2. Notice that LBDRxcomputes the routing bits from the routing restrictionsdefined by the routing algorithm.D. Check Deadlock-Freedom and ConnectivityThe last step of the mapping tool is to verify themapping is deadlock-free and guarantees the connectivityof the initial topology. The routing algorithmapplied in the previous step ensured deadlockfreedombetween 1-hop links, thus, now it must bechecked along 2-hop and 3-hop links. On the otherhand, when applying the routing algorithm and whennot using deroutes, some pair of end nodes may beunconnected. The reason is because LBDRx withoutderoutes relies exclusively on minimal paths. Therefore,a routing restriction may lead to a path beingrouted non-minimally. At this stage, the tool iterateson all the communicating flows of the application(a flow is defined as the path from a producer toa consumer). For each flow, the tool searches a validLBDRx path using the connectivity and routing bitsset by the mapped topology. If for a flow there isno connectivity, then, the mapping is not valid andwe will need either to search a new mapping or usederoutes.On success of a mapping topology, the final outputis the mapping of each switch into the 2D gridand the configuration (connectivity, routing and deroute)bits. Notice that the mapping tool succeeds ifat least one mapping solution is obtained. Also, if nomapping solution exists for a grid size, the mappingtool extends the grid by one row and/or column thushaving much larger flexibility. Figure 2 shows a successfuldeadlock-free mapping for the initial topologydepicted in Figure 1 where connectivity betweenswitches is assured (LBDR3 with deroutes was used).IV. EvaluationIn this section, we provide a comprehensive evaluationof LBDRx. First, we show the results (TableI) of applying the mapping tool to different sets oftopologies with increasing complexity. The mappingtool was run in AMD Opteron (2,8 Ghz dual core,8Gb RAM) computers.Grid size Correct Deroutes TimeType 1 4x4 >10.000 not needed 3-5 mType 2 5X5 >100.000 not needed 10-15 mType 3 5X6 >100.000 not needed 30-45 mType 4 5X7 >100.000 10-15 1-2 hFig. 1 5X7 578.952 13-15 2 hTABLE ITopology mappingsThe main purpose was to compute the number ofcorrect mappings generated for every analyzed topologyand the time required to complete the procedure.In each case, the table shows the minimum grid sizeneeded to map the topology (4x4, 5x5, ..., 5x7), thenumber of correct mappings obtained, and the averagenumber of deroutes used (per mapping), if necessary.Note that correct mappings will be those whichmet the restrictions imposed by the LBDRx versionapplied in each case. In the last column the compu-JP2011-679