Actas JP2011 - Universidad de La Laguna

Actas XXII Jornadas de Paralelismo (JP2011) , La Laguna, Tenerife, 7-9 septiembre 2011Fig. 10.Managing read requests for a private blockherency protocols are defined with the simple definitionof events, actions, and transitions, easily codedin a text-based file and following simple rules. Thenetwork is also defined with many parameters as thetopology, the routing algorithm, and the pipelinedswitch design.gMemNoCsim has been developed to overcome theproblem of long simulation time required by complexsystem-wide environments like GEMS/SIMICS.With gMemNoCsim, memory access traces are usedto speed up simulation time. To keep simulationaccuracy we instrument the traces with the inclusionof memory access dependencies which temporarilyblock processors following synchronization eventsand barriers. As future work we plan to analyzethe impact of memory dependencies computation onsimulation accuracy. Also, we plan to use the platformas an effective tool for network and memoryhierarchy co-design.AcknowlegmentThis work was supported by the Spanish MEC andMICINN, as well as European Commission FEDERfunds, under Grant TIN2009-14475-C04-01. It wasalso partly supported by the project NaNoC (projectlabel 248972) which is funded by the European Commissionwithin the Research Programme FP7.Fig. 11. Managing read requests when a migratory sharingpattern has been detected by the L2 cache bankto the same memory location (variable). Reads andwrites are performed sequentially following the migratorysharing pattern. As can be seen, executiontime is halved by the improved coherency protocol.Indeed, practically all the write operations have beenperformed in the updated protocol in the exclusivemode, thus having exclusive access and not requiringany coherence action to be performed. This translatesalso to half the number of packets injected intothe network.V. ConclusionsIn this paper we have presented the gMemNoCsimsimulator. Memory coherency and on-chip networkcan be co-designed with the new tool as it allows adetailed and accurate modeling of both components.Besides, memory controllers are also modeled. Co-Inv. Inv. with MSCycles 1269949 645099Stores in Shd mode 9999 1Stores in Excl mode 1 9999Injected packets 229997 110021L1 misses 19999 10001L1 hits 1 9999TABLE IIStatistics for two different protocolimplementations in gMemNoCsimReferences[1] Luca Benini, Giovanni De Micheli Networks on chips:technology and tools, Academic Press, 2006.[2] Jose Flich, Davide Bertozzi Designing Network On-ChipArchitectures in the Nanoscale Era, Chapman & Hall/CrcComputational Science Series, 2010.[3] P. S. Magnusson, M. Christensson, and J. Eskilson, et al.Simics: A full system simulation platform., IEEE Computer,35, Feb. 2002. IEEE Computer, 35, 2002.[4] M. M. Martin, D. J. Sorin, and B. M. Beckmann, et al. .Multifacet general execution-driven multiprocessor simulator(GEMS) toolset., Computer Architecture News, 33,2005 .[5] Niket Agarwal, Li-Shiuan Peh and Niraj K. Jha. Garnet:A Detailed Interconnect Model Inside a Full-SystemSimulation Framework, CE-P08-001, Dept. of ElectricalEngineering, Princeton University, 2008.[6] S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta.The SPLASH-2 programs: Characterization and methodologicalconsiderations., 22nd Int. Symp. on ComputerArchitecture (ISCA), 1995.[7] Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singhand Kai Li. The PARSEC Benchmark Suite: Characterizationand Architectural Implications, Proceedings ofthe 17th International Conference on Parallel Architecturesand Compilation Techniques, 2008.[8] Per Stenstrom, Mats Brorsson, Lars Sandberg An adaptivecache coherence protocol optimized for migratory sharing,ISCA ’93 Proceedings of the 20th annual internationalsymposium on computer architecture , 1993.JP2011-580