Calcul des etats atteignables de programmes Esterel partitionne ...

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94 BIBLIOGRAPHY[16] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient Implementation of a BDD Package.In 27th ACM/IEEE Design Automation Conference, pages 40–45, Orlando, Florida, June1990. ACM/IEEE, IEEE Computer Society Press.[17] Yannis Bres. Exploration implicite et explicite de l’espace d’états atteignables de circuitslogiques Esterel. PhD thesis, Ecole des Mines de Paris, December 2002.[18] Randal E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEETransactions on Computers, C-35(8) :677–691, August 1986.[19] Randal E. Bryant. Symbolic Boolean manipulation with ordered binary-decision diagrams.ACM Computing Surveys, 24(3) :293–318, September 1992.[20] J. R. Burch, E. M. Clarke, and D. E. Long. Representing circuits more efficiently in symbolicmodel checking. In ACM-SIGDA ; IEEE, editor, Proceedings of the 28th ACM/IEEE DesignAutomation Conference, pages 403–407, San Francisco, CA, June 1991. ACM Press.[21] J. R. Burch, E. M. Clarke, and D. E. Long. Symbolic model checking with partitionedtransition relations. In A. Halaas and P.B. Denyer, editors, International Conference onVery Large Scale Integration, pages 49–58, Edinburgh, Scotland, August 1991. IFIP Transactions,North-Holland.[22] J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. Symbolic modelchecking for sequential circuit verification. IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems, 13(4) :401–424, April 1994.[23] J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential Circuit VerificationUsing Symbolic Model Checking. In Proceedings of the 27th ACM/IEEE Design AutomationConference, pages 46–51, Los Alamitos, CA, June 1990. ACM/IEEE, IEEE SocietyPress.[24] J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and L. J. Hwang. Symbolic modelchecking : 10 20 states and beyond. In Proceedings, Fifth Annual IEEE Symposium onLogic in Computer Science, pages 428–439, Philadelphia, Pennsylvania, 4–7 June 1990.IEEE Computer Society Press.[25] E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic verification of finite-stateconcurrent systems using temporal logic specifications. ACM Transactions on ProgrammingLanguages and Systems, 8(2) :244–263, April 1986.[26] O. Coudert, C. Berthet, and J. C. Madre. Verification of sequential machines using booleanfunctional vectors. In L.J.M. Claesen, editor, Proceedings of the IFIP International WorkshopApplied Formal Methods for Correct VLSI Design, pages 111–128, Leuven, Belgium,November 1989. North-Holland.[27] O. Coudert, C. Berthet, and J. C. Madre. Verification of synchronous sequential machinesusing symbolic execution. In Proceedings of the International Workshop on AutomaticVerification Methods for Finite State Systems, volume 407 of Lecture Notes in ComputerScience, pages 365–373, Grenoble, France, June 1989. Springer-Verlag.[28] O. Coudert and J. C. Madre. A unified framework for the formal verification of sequentialcircuits. In Satoshi Sangiovanni-Vincentelli, Alberto ; Goto, editor, Proceedings of the IEEEInternational Conference on Computer-Aided Design, pages 126–129, Santa Clara, CA,November 1990. IEEE Computer Society Press.[29] O. Coudert and J. C. Madre. Symbolic computation of the valid states of a sequentialmachine : algorithms and discussion. In ACM Workshop on Formal Methods in VLSIDesign, 1991. Miami.
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RemerciementsJe remercie le monde e
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Thèse1
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1.2. NOTRE APPROCHE 51.2 Notre appr
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1.4. TRAVAUX RELIÉS 7l’hypothès
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Chapitre 2Contexte de l’EtudeCe c
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2.4. CALCUL SYMBOLIQUE DES ÉTATS A
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2.5. LES DIAGRAMMES DE DÉCISION BI
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28 CHAPITRE 2. CONTEXTE DE L’ETUD
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30 CHAPITRE 2. CONTEXTE DE L’ETUD
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3.1. DESCRIPTION GÉNÉRALE DE LA M
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38 CHAPITRE 3.PRÉSENTATION INTUITI
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3.3. PARTITIONNEMENT DES BOUCLES 41
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Page 66 and 67: 58 CHAPITRE 4. NOTATIONSalors Surfa
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Page 70 and 71: 62 CHAPITRE 5. CALCUL DES ETATS ATT
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Page 96 and 97: 88 CHAPITRE 7. EXPÉRIMENTATIONS7.3
Page 98 and 99: 90 CHAPITRE 7. EXPÉRIMENTATIONS
Page 100 and 101: 92 CHAPITRE 8. CONCLUSION ET PERSPE
Page 104 and 105: 96 BIBLIOGRAPHY[47] Alan J. Hu and
Page 106: 98 BIBLIOGRAPHY[77] Herve J. Touati
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