Calcul des etats atteignables de programmes Esterel partitionne ...

96 BIBLIOGRAPHY[47] Alan J. Hu and David L. Dill. Reducing BDD size by exploiting functional dependencies.In Design Automation Conference, pages 266–271, 1993.[48] Alan J. Hu, Gary York, and David L. Dill. New techniques for efficient verification with implicitlyconjoined BDDs. In Michael Lorenzetti, editor, Proceedings of the 31st Conferenceon Design Automation, pages 276–282, New York, NY, USA, June 1994. ACM Press.[49] C. Norris Ip and David L. Dill. Better verification through symmetry. Formal Methods inSystem Design : An International Journal, 9(1/2) :41–75, August 1996.[50] S. Iyer, D. Sahoo, Ch. Stangier, A. Narayan, and J. Jain. Improved symbolic verificationusing partitioned techniques. pages 410–424. LNCS 2860, 2003.[51] J. Jain, J. Bitner, D. S. Fussell, and J. A. Abraham. Functional partitioning for verificationand related problems. In Advanced Research in VLSI and Parallel Systems : Proceedingsof the 1992 Brown/MIT Conference, pages 210–226, 1992.[52] Gila Kamhi and Limor Fix. Adaptive Variable Reordering for Symbolic Model Checking. InProceedings of the International Conference on Computer-Aided Design, ICCAD’98. ACMPress, November 1998.[53] P. Le Guernic, T. Gauthier, M. Le Borgne, and C. Le Maire. Programming real-timeapplications with signal. In Proceedings of the IEEE, volume 79(9), pages 1321–1336, 1991.[54] C. Y. Lee. Representation of switching functions by binary decision programs. Bell SystemsTechnical Journal, 38 :985–999, 1959.[55] J. C. Madre and J. P. Billon. Proving circuit correctness by formally comparing theirexpected and extracted behavior. In 25th Design Automation Conference, Anaheim, June1988.[56] Sharad Malik, Albert Wang, Robert Brayton, and Alberto Sangiovanni-Vincentelli. LogicVerification Using Binary Decision Diagrams in a Logic Synthesis Environment. In Proceedingsof the International Conference on Computer Aided Design, ICCAD’88, November1988.[57] Florence Maraninchi. The Argos Language : Graphical Representation of Automata andDescription of Reactive Systems. In Proceedings of the IEEE Workshop on Visual Languages,October 1991.[58] K. L. McMillan. The SMV system, symbolic model checking - an approach. TechnicalReport CMU-CS-92-131, Carnegie Mellon University, 1992.[59] George H. Mealy. A method for synthesizing sequential circuits. Bell System TechnicalJournal, 34(5) :1045–1079, 1955.[60] Christoph Meinel and Christian Stangier. Speeding Up Image Computation by Using RTLInformation. In Formal Methods in Computer-Aided Design, FMCAD’00, volume 1954 ofLecture Notes in Computer Science, pages 443–454. Springer, November 2000.[61] Christoph Meinel and Christian Stangier. A New Partitioning Scheme for Improvement ofImage Computation. In Proceedings of Asia South Pacific Design Automation Conference(ASPDAC’01), pages 97–102. ACM Press, January 2001.[62] In-Ho Moon, Gary D. Hachtel, and Fabio Somenzi. Border-Block Triangular Form andConjunction Schedule in Image Computation. In Proceedings of the 3rd InternationalConference on Formal Methods in Computer-Aided Design, FMCAD’00, volume 1954 ofLecture Notes in Computer Science, pages 79–90. Springer, November 2000.