Script for Laboratory: Designing embedded ASIPs - CES

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y Hennessy and Patterson, is using a data forwarding technique to resolve such data dependencies without the in-between NOPs, but ASIP Meister does not support data forwarding in the current release 1.1. Therefore, for ASIP Meister generated processors the NOPs are needed to resolve the data dependencies (as shown in Chapter 3.2.1 you can configure dlxsim to behave in both ways, i.e. with or without data forwarding). Overlapping Overlapping Execution Execution of of multiple multiple Commands Commands with with a a data data dependency dependency r1 r1 = = r2 r2 + + r3 r3 nop nop nop nop nop nop r4 r4 = = r5 r5 + + r1 r1 IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB Figure 3-1 DLX pipeline example with a data dependency IF IF Instruction IF Instruction Fetch IF Instruction Fetch Instruction Fetch ID Fetch ID Instruction ID Instruction Decode ID Instruction Decode Instruction Decode EXE Decode EXE Execute EXE Execute EXE Execute MEM Execute MEM Memory MEM Memory Access MEM Memory Access Memory Access WB Access WB Write WB Write Back WB Write Back Write Back Back Cycle Cycle number: number: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 Under some special circumstances, less than three NOPs might be enough to resolve a data dependency. Such an example is shown in Figure 3-2. In this example, the multicycle instruction LW (Load Word) has been used and this instruction might force the pipeline to stall. How long the pipeline is stalled and whether it is stalled at all, relies on the speed of the used data memory. If the cache can handle a load instruction, then the pipeline might not stall at all, but if slow memory is used, then the pipeline might stall for some dozen cycles. Figure 3-3 shows how important it is to know, when exactly the pipeline is going to be stalled. The only difference between Figure 3-1 and Figure 3-2 is the order of the NOP and the LW instruction. With the LW instruction as first instruction, the stall happens just in time to resolve the data dependency. With the NOP instruction first, the stall comes too late. This shows how carefully one has to deal with pipeline stalling when manually optimizing assembly code. - 18 -
Successful Successful dissolving dissolving a a data data dependency dependency with with a a load load instruction instruction IF IF Instruction IF Instruction Fetch IF Instruction Fetch Instruction Fetch ID Fetch ID Instruction ID Instruction Decode ID Instruction Decode Instruction Decode EXE Decode EXE Execute EXE Execute EXE Execute MEM Execute MEM Memory MEM Memory Access MEM Memory Access Memory Access WB Access WB Write WB Write Back WB Write Back Write Back Back Cycle Cycle number: number: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 r1 r1 = = r2 r2 + + r3 r3 lw lw nop nop r4 r4 = = r5 r5 + + r1 r1 IF IF (stall) ID ID IF IF (stall) ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB Figure 3-2 Successful dissolving a data dependency with a load instruction Cycle Cycle number: number: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 r1 r1 = = r2 r2 + + r3 r3 nop nop lw lw Unsuccessful Unsuccessful dissolving dissolving a a data data dependency dependency with with a a load load instruction instruction r4 r4 = = r5 r5 + + r1 r1 IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB IF IF ID ID IF IF ID EXE EXE (stall) MEM WB WB ID EXE EXE (stall) MEM WB WB IF IF ID ID IF IF ID (stall) EXE EXE MEM WB WB ID (stall) EXE EXE MEM WB WB IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB IF IF ID ID IF IF ID EXE EXE MEM WB WB ID EXE EXE MEM WB WB IF IF Instruction IF Instruction Fetch IF Instruction Fetch Instruction Fetch ID Fetch ID Instruction ID Instruction Decode ID Instruction Decode Instruction Decode EXE Decode EXE Execute EXE Execute EXE Execute MEM Execute MEM Memory MEM Memory Access MEM Memory Access Memory Access WB Access WB Write WB Write Back WB Write Back Write Back Back IF IF ID ID IF IF ID EXE (stall) MEM WB WB ID EXE (stall) MEM WB WB IF IF ID ID IF IF ID (stall) EXE MEM WB WB ID (stall) EXE MEM WB WB Figure 3-3 Unsuccessful dissolving a data dependency with a load instruction - 19 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 21 and 22: Instruction Description Instruction
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70:
8 CoSy compiler The CoSy compiler d
Page 71 and 72:
When you manually have to fix some
Page 73 and 74:
of the makeCoSy script. If an error
Page 75 and 76:
the automatically generated compile
Page 77 and 78:
instruction, as different custom in
Page 79 and 80:
Directive Explanation .restrict .ch
Page 81 and 82:
Now we will demonstrate how you can
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the user changes the value of the b
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• Huge decrease of cycle count
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of instructions together it might t
Page 89 and 90:
Table of Figures Figure 1-1 GPPs, A
Page 91:
References [CES] Homepage of the Ch
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