Script for Laboratory: Designing embedded ASIPs - CES

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The instruction set of the DLX architecture is separated into 4 instruction classes (arithmetic for integer, arithmetic for float, load/store and branch), which are implemented in 3 instruction formats, as shown in Figure 3-4. The arithmetic instructions use either an instruction format for three registers or an instruction format for two registers and an immediate value. The load/store instructions always use the format with two registers and one immediate, where the effective address is compute as the sum of one register (as base address) and the immediate. The other register is used either as value to store or as register where to save the loaded value. The branch instructions are divided into conditional branches and unconditional jumps. The jumps always use an instruction format with a 26-bit immediate, so they have a big PC-relative jump-target. The conditional branches need a field for a register that contains the condition, so they restrict to a 16-bit immediate. The second available register in the format for branches is not used by the branch instructions. Instruction-formats Instruction-formats Instruction-classes Instruction-classes 6 5 5 5 11 6 5 5 5 11 R-Format: Opcode rs1 rs2 rd func R-Format: Opcode rs1 rs2 rd func 6 5 5 16 6 5 5 16 I-Format: Opcode rs1 rd Immediate I-Format: Opcode rs1 rd Immediate 6 26 6 26 J-Format: Opcode Offset J-Format: Opcode Offset Arithmetic Arithmetic instructions Arithmetic instructions for Arithmetic instructions for integers instructions for integers for integers integers Arithmetic Arithmetic instructions Arithmetic instructions for Arithmetic instructions for floating instructions for floating points for floating points floating points points Load Load and Load and store Load and store instructions and store instructions store instructions instructions Branch Branch instructions Branch instructions Branch instructions instructions Figure 3-4 Instruction formats and classes of the DLX architecture For many assembly-commands, there are special versions for dealing with unsigned values and for using immediate values as seconds input parameters. Those versions have an attached “i” for “immediate” and/or an attached “u” for “unsigned” as suffix (e.g. addui). A summary of all assembly instructions that are available in the ASIP Meister specific implementation of the DLX processor that is used in the laboratory (i.e. dlx_basis) is shown in Figure 3-5. For a more detailed description of the assembly-commands have a look into [Sailer96]. - 20 -
Instruction Description Instruction Description add, addu, addi, addui Add; Syntax: add rd rs0 rs1; rs1 can alternatively be the immediate sub, subu, subi, subui Subtract mult, multu Multiply div, divu Divide mod, modu Modulo and, andi And or, ori Or xor, xori Xor sll, slli Shift left logical srl, srli Shift right logical Set “less than”; Syntax: slt sra, srai Shift right arithmetic slt, sltu, slti rd rs0 rs1; Compare rs0 and rs1 and set rd to 1 if and only if rs0 is “less than” rs1 sgt, sgtu, sgti Set “greater than” sle, slue, slei Set “less or equal” sge, sgeu, sgei Set “greater or eaqual” seq, seqi Set “equal” Load high immediate; Syntax: lhi rd imm; Load an 16-bit sne, snei Set “not equal” lhi immediate into the 16 high bits of an register; use together with “ori” to load an 32-bit immediate lb, lbu Load Byte lh, lhu Load High lw Load Word; Syntax: load rd, imm(rs); the effective address is computed by adding the immediate to rs sb Store Byte; Syntax: store imm(rd), rs; the effective address is computed by adding the immediate to rd sh Store High Branch if “equal zero” Syntax: branch rs, imm; sw Store Word beqz the branch target is a PCrelative address, given by the immediate bnez Branch if “not equal zero” Jump (register); Syntax: j Jump and link (register); imm; jr rs; The jump target Similar to j/jr, but also writes j, jr is a PC-relative address, given jal, jalr the address from the following by the immediate or the command to the link register; register Figure 3-5 used for subroutines Summary of all assembly instructions in the dlx_basis processor - 21 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19: Successful Successful dissolving di
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
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When you manually have to fix some
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of the makeCoSy script. If an error
Page 75 and 76:
the automatically generated compile
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instruction, as different custom in
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Directive Explanation .restrict .ch
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Now we will demonstrate how you can
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the user changes the value of the b
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• Huge decrease of cycle count
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of instructions together it might t
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Table of Figures Figure 1-1 GPPs, A
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References [CES] Homepage of the Ch
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