Script for Laboratory: Designing embedded ASIPs - CES

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Error Messages while Software Generation: • “13 1 or 0 required in const value”: (the value “13” is exemplary) Make sure, that your signal assignments in the MicroOp Description contain space characters, like: “flag='0';”, with standing as a placeholder for a space character. • “The format of the instruction "slli" does not have all of elements. "none" is missed.”: (the instruction name “slli” is exemplary) In the Instruction Definition for an Instruction Type do not use the Field Type "Reserved" with the Field Attribute "binary". Error Messages in Hardware OR Software Generation OR anywhere else in ASIP Meister: • “Out of Memory”: Make sure, that your signal assignments in the MicroOp Description contain space characters, like: “flags="0000";”, with standing as a placeholder for a space character. • “Keyword error: "don't_care" is not name or binary”: This message can appear in the “Arch. Level Estimation”. In the Instruction Definition for an Instruction Type do not use the Field Type "Reserved" with the Field Attribute "don’t care". Error Messages outside ASIP Meister, but inside our tool chain • You have to write blanks in the MicroOp description, e.g. "result=ALU.add", with standing as a placeholder for a space character. If you write it like "result=ALU.add", meistercg will complain about something like "LU.add" (the “A” is missing in this error message), while creating the CoSy compiler. • “ERROR: IOException while reading from inputFile or writing to outputFile. "null" Aborting execution now.”: This message can appear while running the tool “ASIP_asm”, which is a part of the mkimg scripts. The reason for this message is an unusual character in the input file of ASIP_asm, i.e. the *.out file from compiler_temp. To remove this unusual sign, just open the *.out file in a text editor and copy everything into a new file. This new file should no longer contain the unusual sign. A ‘diff’ will show you the line in which the sign was placed. Now you manually have to give this modified *.out file as input to ASIP_asm to receive the TestData files. Usually this happens, if you work with hand written assembly code and the unusual sign already existed in the original assembly file. Then you better remove this sign with the described method, like for the *.out file. - 34 -
4.3 Tutorial for the “Flexible Hardware Model” (FHM) To add a new instruction to an ASIP Meister CPU one would usually write a MicroOp description for the instruction, using the facilities of an existing hardware module (ALU, shifter, adder, etc). The ability to use multiple hardware modules during one stage and to create more than one instance of a specific module combined with the operators provided by the MicroOp description language is sufficient for most basic instructions. However, this method has several shortcomings that make it impossible to do the following (among others): • Working with not program-defined wire ranges which depend on register contents or immediate values • Implementing multi-cycle instructions This tutorial will show how to write a new hardware module to provide a "rotate left" instruction. Setting up ASIP Meister In our current setup, ASIP Meister is installed globally. To modify FHMs you will need to set it up locally: 1. Copy the ASIP Meister directory tree to your home directory: cp -r /usr/epp/ASIPmeister/ ~ 2. Update the PATH environment variable to use the local ASIP Meister directory by editing the file .bashrc.user and adding the following line at the end of the file: PATH=$HOME/ASIPmeister/bin/:$PATH 3. Force the shell to re-read the rc file to use the updated PATH variable: source ~/.bashrc or logout and login again 4. Verify that you are using the correct ASIP Meister copy: which ASIPmeister should print the path to the local copy 5. Edit ~/ASIPmeister/bin/ASIPmeister (line 25) and make sure your local ASIP Meister path ($HOME/ASIPmeister) is assigned to the variable ASIP_MEISTER_HOME. From now on whenever relative paths (not starting with a /) are mentioned, $HOME/ASIPmeister shall be the base directory, i.e.: share/fhmdb/workdb/peas/rotator.fhm would be /home/asipXX/ASIPmeister/share/fhmdb/workdb/peas/rotator.fhm FHM structure The directory share/fhmdb has two subdirectories and the file fhmdbstruct. ASIP Meister reads this file to determine which FHM files to use. Most of the modules necessary for the basic functions of the CPU are in the directory basicfhmdb; they are further divided into the categories computational and storage. New FHMs should be added to the share/fhmdb/workdb/peas directory. - 35 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19 and 20: Successful Successful dissolving di
Page 21 and 22: Instruction Description Instruction
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33: • If you manually want to write a
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
Page 73 and 74: of the makeCoSy script. If an error
Page 75 and 76: the automatically generated compile
Page 77 and 78: instruction, as different custom in
Page 79 and 80: Directive Explanation .restrict .ch
Page 81 and 82: Now we will demonstrate how you can
Page 83 and 84: the user changes the value of the b
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• Huge decrease of cycle count
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of instructions together it might t
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Table of Figures Figure 1-1 GPPs, A
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References [CES] Homepage of the Ch
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