Script for Laboratory: Designing embedded ASIPs - CES

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9.2 Speedup calculation t1 t1 t1 2 2 Cycles 2 Cycles 2 Cycles Cycles 3 3 Cycles 3 Cycles 3 Cycles Cycles 1 1 Cycle 1 Cycle 1 Cycle Cycle px_5 px_5 px_5 2 2 Cycles 2 Cycles 2 Cycles Cycles y_3 y_3 y_3 Figure 9-2 Rough estimated cycle counts for the custom instruction Figure 9-3 A custom instruction with control structure A very easy example to show the speed up of an application has been shown in the Figure 9-2. We have taken a very simplistic assumption for calculating the speedup. Load takes two cycles, multiplication takes 3 cycles and an addition takes one cycle. The custom instruction shown in Figure 9-1 should take 8 software cycles but if we implement this group - 86 -
of instructions together it might take 6 hardware cycles because of inherent instruction parallelism. The number of execution of this instruction can be calculated through profiling. Then we basically can calculate the speed up for this instruction in number of cycles. But it is worth mentioning that this new instruction may increase the latency or may increase the area of the processor unmanageably. There are also few open questions in this example i.e. whether it is easy to implement memory operation in the custom instruction. We have to also take the penalty of implementing custom instruction with local memory operation. It is also a very interesting research area. Figure 9-4 A very complex custom instruction - 87 -
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Laboratory: “Designing Applicatio
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6 Validating the CPU in Prototyping
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Figure 1-1 GPPs, ASIPs and ASICs [H
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• Command line interpreter Intera
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i. Copying files: the cp command co
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. Copying via ssh: Not all machines
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dlx_basis Applications ModelSim mei
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makeCoSy contCoSy Filename Explanat
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3 Dlxsim Dlxsim [DLX-Package] is an
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Successful Successful dissolving di
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Instruction Description Instruction
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Option Description -dbb# (Debug Bas
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Instruction Format Parameters NO_AR
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Command Description stop {options}
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3.3.2 Debugging with dlxsim This ch
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addComment1(); functionY(); addComm
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• If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
Page 73 and 74: of the makeCoSy script. If an error
Page 75 and 76: the automatically generated compile
Page 77 and 78: instruction, as different custom in
Page 79 and 80: Directive Explanation .restrict .ch
Page 81 and 82: Now we will demonstrate how you can
Page 83 and 84: the user changes the value of the b
Page 85: • Huge decrease of cycle count
Page 89 and 90: Table of Figures Figure 1-1 GPPs, A
Page 91: References [CES] Homepage of the Ch
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Script for Laboratory: Designing embedded ASIPs - CES

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