Script for Laboratory: Designing embedded ASIPs - CES

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Instead of the sub window shown in Figure 5-2 when creating a new project, you can use the menu: File > Add to Project > Existing File. 5.1.4 Run the simulation Menu: Simulate > Start Simulation Figure 5-3 Compiling the project Open the work library, mark the entry cfg (that’s the VHDL configuration <strong>for</strong> the testbench) in the list as shown in Figure 5-4 and press OK. That will start the simulation and you will get another two tabs attached to the Workspace window (sim / Files). IMPORTANT: Make sure that no Component Unbound Message is printed while starting the simulation. If such a message is printed, then this is a serious problem within the simulation. Usually it helps to recompile everything and to start the simulation again (menu: Compile > Compile All). But a new VHDL file, that was automatically created by ASIP Meister, but that is not included into your project yet, can also cause such a message. Menu: Tools > Execute Macro - 48 -
Mark the wave.do file in your ModelSim directory and press OK to load it. The wave-window gets filled with certain signals that are useful to evaluate the simulation of the program running on the processor. Those signals are explained in Chapter 5.1.5. Figure 5-4 Starting the ModelSim simulation Press the button Run all to run the simulation until it aborts. At the end of a simulation the message “Failure: Simulation End” is printed. The type “Failure” is only used to automatically abort the simulation. This is not a real failure. At the simulation end the file Test- Data.OUT is created in your ModelSim directory. It contains the content of the simulated memory after the CPU finished working. So if your algorithm is storing the result in the memory you can find the values here. If you want to run another simulation with a changed program or with a changed initial data memory, then all you have to do is to run mkimg to create the new TestData.IM and Test- Data.DM and afterwards you have to press the buttons restart and run all, like shown in Figure 5-5. - 49 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19 and 20: Successful Successful dissolving di
Page 21 and 22: Instruction Description Instruction
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47: 5.1.3 Compile the project Figure 5-
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
Page 73 and 74: of the makeCoSy script. If an error
Page 75 and 76: the automatically generated compile
Page 77 and 78: instruction, as different custom in
Page 79 and 80: Directive Explanation .restrict .ch
Page 81 and 82: Now we will demonstrate how you can
Page 83 and 84: the user changes the value of the b
Page 85 and 86: • Huge decrease of cycle count
Page 87 and 88: of instructions together it might t
Page 89 and 90: Table of Figures Figure 1-1 GPPs, A
Page 91: References [CES] Homepage of the Ch

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