Script for Laboratory: Designing embedded ASIPs - CES

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• As soon as a new FHM is successfully constructed, you can make further changes directly in the VHDL code for simplicity. Whenever the VHDL code is finalized, you should include it into the FHM file again, as the created VHDL files are overwritten every time you regenerate your CPU. • Create backups very frequently. Due to the difficult debugging, it is difficult to find and fix bugs and thus it is often simpler to go back to a slightly earlier version and to implement the changes again. - 44 -
5 ModelSim ModelSim is a full-featured VHDL simulator. With VHDL you can create logic designs consisting of any size. To verify functional operation you need to simulate your design to see whether it works like expected. Therefore test benches are used. They contain so-called stimuli or test vectors, simply said: values for the input signals. Those values are applied to the input signals and then the corresponding output signals are compared with the expected values. To simulate a specific design one has to provide two kinds of files to the ModelSim simulator: VHDL files that contain your processor design and a testbench file that creates the needed environment. ASIP Meister is creating the VHDL files for your processor design automatically and the designer doesn’t have to take care about the VHDL implementation of the processor. We provide the testbench and you can find it in the TEM- PLATE_PROJECT/ModelSim directory (directory structure is explained in Chapter 2.3). This testbench is providing a reset and a clock signal to the CPU. Furthermore it contains simulated data- and instruction-memory for the CPU. Those simulated memories have to be initialized with memory images that are read from TestData.DM and TestData.IM, before the CPU can start executing the application. The mkimg script is creating those memory images and it automatically copies them to the ModelSim directory of your current ASIP Meister project (so you are always simulating the application, that was compiled last). After the simulation of the application is finished you will find a memory image of the final data memory (TestData.OUT) that contains the results of the application if they are stored in data memory. 5.1 Tutorial 5.1.1 Create a new ModelSim Project Please be aware that it is important that you start ModelSim in the ModelSim directory of your ASIP Meister project, as it is shown in Chapter 2.3. On the shell change to the ModelSim directory of your project and invoke “vsim &”. If ModelSim asks for modelsim.ini choose the default.ini to proceed. Menu: File > New > Project Enter a project name and change the project location to the ModelSim directory in your project directory. Confirm the dialog with the OK button. - 45 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19 and 20: Successful Successful dissolving di
Page 21 and 22: Instruction Description Instruction
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43: data_in : in std_logic_vector($W1 d
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
Page 73 and 74: of the makeCoSy script. If an error
Page 75 and 76: the automatically generated compile
Page 77 and 78: instruction, as different custom in
Page 79 and 80: Directive Explanation .restrict .ch
Page 81 and 82: Now we will demonstrate how you can
Page 83 and 84: the user changes the value of the b
Page 85 and 86: • Huge decrease of cycle count
Page 87 and 88: of instructions together it might t
Page 89 and 90: Table of Figures Figure 1-1 GPPs, A
Page 91: References [CES] Homepage of the Ch

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