Script for Laboratory: Designing embedded ASIPs - CES

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e used to assign values to variables. No additional signals are necessary for our rotator, so we will leave $signals as it is. The next variable, $vhdl is more interesting: Our module should be sensitive to changes of input data, shifting amount and shifting direction (so it should recompute the output data if one of these three values changes), hence we define a process with those three values in its sensitivity list. We also need one integer variable to hold the value of the shifting amount (amount is a signal, not a variable) and one signal for the temporary value of the result. After the begin keyword we can write the process code. First, we need to convert the signal amount to integer and assign it to a. Next we check if a is within range, if it isn't, we set the result to undefined, otherwise we can rotate. A case switch is used to decide into which direction to rotate. The others case is necessary, as the type std_logic has more states than just '0' and '1', so don't delete it when you add the code for "rotate right". At the end of the process, we assign the value of the res signal to the data_out signal. See the below listing for the architecture VHDL: process (data_in, amount, direction) variable a : integer; variable res : std_logic_vector($msb downto 0); begin a := TO_INTEGER(UNSIGNED(amount)); if (a > 0 and a < $bit_width) then case direction is when '0' => -- rotate left res($msb downto a) := data_in($msb - a downto 0); res(a - 1 downto 0) := data_in($msb downto $bit_width - a); when others => -- not reached res := (others => 'X'); end case; else res := (others => 'X'); end if; data_out
amount : in std_logic_vector(7 downto 0); data_out : out std_logic_vector($msb downto 0) That is it for the block. Next, we have an section. It defines an entity in a different file, which is why a new block is needed, but the ports are the same, so use the code from the above listing. Estimation and the Synthesis model The section can be left empty, the script contains instructions to process the FHM file - we leave that untouched as well. The block has data relevant for area, power and delay estimations, but we use more accurate tools, that consider the actual application execution, as shown in Chapter 6.4, Chapter 6.5 and Chapter 7.2. Leave the estimation data there though, as ASIP Meister will complain without them. Should you change FHM parameters however, you will have to adjust the estimation section if you want to get rid of the warnings. That is it for the behavior model. As mentioned in the beginning, we won't differ between the behavior and the synthesis model, so just copy/paste the complete block and change the value of the tag from behavior to synthesis. Your FHM file should now have a structure similar to the following listing: rotator behavior [...] synthesis [...] You can now use the module in ASIP Meister. Instantiate the FHM resource in the Resource Declaration and write the new instruction rotl. Set the operands to the correct Addressing Mode, DataType, etc in the Behavior Description window, but leave the behavior description itself out. Use the syntax result = ROT0.rotl(source0, am); where result and source0 are 32-bit wires and am is a 8-bit wire. - 39 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19 and 20: Successful Successful dissolving di
Page 21 and 22: Instruction Description Instruction
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37: in direction; The in keyword means
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
Page 73 and 74: of the makeCoSy script. If an error
Page 75 and 76: the automatically generated compile
Page 77 and 78: instruction, as different custom in
Page 79 and 80: Directive Explanation .restrict .ch
Page 81 and 82: Now we will demonstrate how you can
Page 83 and 84: the user changes the value of the b
Page 85 and 86: • Huge decrease of cycle count
Page 87 and 88: of instructions together it might t
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Table of Figures Figure 1-1 GPPs, A
Page 91:
References [CES] Homepage of the Ch
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Script for Laboratory: Designing embedded ASIPs - CES

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