Script for Laboratory: Designing embedded ASIPs - CES

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Finally, some specialties in the architecture need to be mentioned: • Delay slots: An instruction, that is placed right after an unconditional jump or a conditional branch instruction is always executed. In fact, there are two instructions, that enter the pipeline, but only the first one is executed, the second one will not be allowed to write the computed result back to the register file. • Multicycle operations: The operations mult, div and mod in their different versions are multicylce operations. That means, that those operations will not stay for one cycle in the execute phase, but for multiple cycles. The pipelined is stalled until the instructions finished their work in the execute stage. • Stalling: The communication to the data memory is controlled by Request/Acknowledge- Signals to deal with memories of different speed. The corresponding assembly instructions might stay for multiple cycles in the memory stages, until the memory access is finished. • Special Registers: Some registers in the general-purpose register file usually handle some special cases. However, contrary to the hard-wired zero-register r0 any register, as long it is done consistent in the assembly file, can handle those other special cases. Those special cases are the stack pointer (r29), the frame pointer (r30) and the link register (r31), which is then used as return address. 3.2 Extending dlxsim 3.2.1 Configuring dlxsim Some parameters can be adapted when starting dlxsim. All mentioned parameters in Figure 3-6 do not allow blanks between a parameter and a possible value, e.g. “-pd1” instead of “-pd 1”. -ms# (Memory Size) -ffilename Option Description -da# (Debug Assembly) The size of the memory that is available within dlxsim. It is the common memory for instructions and data. This parameter will load an assembly file after initialization. This parameter is equivalent to the instruction “load {filename}” in Figure 3-8. This option helps you debugging the simulated assembly code. A debugging output is printed for all load/store and jump/branch instructions, including in which cycle the message was printed and from which address it was triggered. By default, this option is turned on. To turn it off you have to enter “-da0”. - 22 -
Option Description -dbb# (Debug Base Blocks) -cdd# (Check Data Dependency) -wsdo# (Warn Specific Dependency Once) -pd# (Pipeline Delay) -pffilename This option only has an effect, if the before mentioned option “Debug Assembly” is enabled too. If both options are activated, then a register snapshot will automatically be printed at every base block start. This snapshot only includes registers, for which the value has changed since the last snapshot. By default, this option is turned off to avoid the enormous amount of output. To turn it on you have to enter “-dbb1”. With this option, you enable a warning message that appears when an unresolved data dependency is found in the executed assembly code. This means you will get a warning if for example, r5 is read in cycle 10, but an earlier command has made a write access to r5, that cannot be read back before cycle 12. So you would read the ‘old’ value. By default, this option is turned on. To turn it off you have to enter -cdd0. This option belongs to the before mentioned option Check Data Dependency. If there is an unresolved data dependency in a loop, then the warning message would usually be printed for every time the loop is executed. With this define the warning will only be printed the first time the unresolved data dependency is noticed. By default, this option is turned on. To turn it off you have to enter –wsdo0. With this option, you can configure, whether a delayed register writeback shall be emulated and if yes, how long the delay between register write and register read shall be. The internal usage of this value is like this: If a value is written in cycle c, then it cannot be read back before cycle c + PipelineDelay. For the laboratory there are two useful values: With the value 1 you configure, that only the elementary delay shall be assumed. That means, that the result of an instruction can immediately be read back by the succeeding instruction. This can be imagined, like a pipeline model with a data-forwarding concept. Remember, that the delay-slots for branches are still used! With the value 4 you configure the pipeline model that is used for the ASIP Meister generated processor with the register read in stage 2 and the register write in stage 5. This can be imagined like a pipeline model without a data-forwarding concept. Other values except 1 and 4 are basically working too, but the instructions, that imply a pipeline stall (e.g. load, mult, …) are personalized to the values 1 and 4 and might behave unexpected for different values. The default value is 4. With this parameter, all print instructions (as shown in Chapter 8.5.1) are written to a file instead of the screen. Figure 3-6 Summary of helpful dlxsim starting parameters Legend: cursive: replace with appropriate option #: replace with a number - 23 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19 and 20: Successful Successful dissolving di
Page 21: Instruction Description Instruction
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
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of the makeCoSy script. If an error
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the automatically generated compile
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instruction, as different custom in
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Directive Explanation .restrict .ch
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Now we will demonstrate how you can
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the user changes the value of the b
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• Huge decrease of cycle count
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of instructions together it might t
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Table of Figures Figure 1-1 GPPs, A
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References [CES] Homepage of the Ch
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