Script for Laboratory: Designing embedded ASIPs - CES

Signal Explanation
im_data This is the Instruction Memory Data that corresponds to the previous
shown im_addr. So it’s the binary representation of the assembly
instruction that is fetched by the CPU.
w_enb0 This is the write-enabled signal. It controls, whether the data at the
input port of the register file will be written to the specified register or
not. For example while jump or multicycle instructions this value is
partially disabled (i.e. value ‘0’). Especially the jump instructions
create a typical pattern for this signal. The jump instruction itself does
not write to the register file, so this signal is ‘0’ when the jump
instruction comes to its WB phase. The 2 instructions after the jump
instruction enter the pipeline, but only the first one will be allowed to
write its result back to the register file.
w_sel0 This signal selects to which register the value at the input port of the
register file shall be written.
data_in0 This is the data value that is going to be written into the register file, if
the write-enabled signal is active.
r_selX This signal selects which register of the register file shall be read.
data_outX This is the data value that was read from the requested register.
dataab This is the Address Bus for memory accesses. This bus either contains
the address to which some data shall be written or the address from
which some data shall be read.
datadb The Data Bus contains the value that shall be written or that was read.
datareq This is the request signal with which the CPU triggers a read or a write
access.
dataack This is the acknowledge signal, that is activated by the memory
controller after a requested write access is finished or after the data bus
contains the result of a requested read access.
datawin This signal determines the write mode. The usual values are “1111” for
“read word” and “0000” for “write word”, but there are also values for
writing 8- and 16-bit values.
Figure 5-7
Explanation of the signals in the ModelSim wave
5.2 General hints
• Change to your ModelSim directory inside your project directory tree and verify that
the memory images TestData.IM and TestData.DM are present. They were build by
mkimg. Furthermore you need the testbench file tb_ASIPmeister.vhd and the Model-
Sim configuration script wave.do, which are available in the TEM-
PLATE_PROJECT/ModelSim directory. Please check their existence in your Model-
Sim directory before you start the work. It keeps you away from trouble.
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