Script for Laboratory: Designing embedded ASIPs - CES

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Figure 6-3 Add Sources Figure 6-4 ISE project overview - 56 -
CPU VHDL Files have been generated using ASIP Meister and they can be found in the meister/{CPU-Name}.syn directory, as explained in Chapter 2.3. Framework Files are important for the connection between CPU, Memory, LCD and all other components. They are pre designed for this laboratory and they are available in ~asip00/ASIPMeisterProjects/TEMPLATE_PROJECT/ISE_Framework. The framework consists of the following three types of file and all of them have to be added to the ISE project. • The VHDL files describe how all components are connected together. • The UCF file describes the user constraints (e.g. which I/O pins should be used, which clock frequency is requested). • The BMM file contains a description of the memory buildup for instruction- and datamemory for the CPU. Out of this file …_bd.bmm file will be generated while implementation and this file is then used to initialize the created bitstream with the application data, as explained in Chapter 6.3. IP cores are used within the framework, e.g. memory blocks for instruction- and datamemory or FIFOs for the connection to the LCD. These IP cores are not available as VHDL source code, but instead they are available as pre-synthesized net lists. These files just have to be available inside the directory of your ISE project (no need to actually ‘add’ them to the project) and then they will be used in the implementation step. The needed files (*.edn, *.ngc) are available in ~asip00/ASIPMeisterProjects/TEMPLATE_PROJECT/ISE_Framework. After you have added all needed files to your ISE project/directory, your main window should look similar to the screenshot shown in Figure 6-4. In the sources sub window you can see all the source files and how they are structured, i.e. which file is instantiating which other file. The other sub windows will be explained in Chapter 6.2. 6.2 Synthesizing and implementing the ISE project In the Processes sub window in the lower left corner of Figure 6-4 the possible actions for each kind of file is shown. To synthesize and to implement your project you have to choose your VHDL-Toplevel in the Sources sub window (“dlx_Toplevel” in the figure) and afterwards you have to double click “Generate Programming File” in the Processes sub window. This will finally create the .bit file, that can then be initialized with your CPU instruction- and data-memory and afterwards be uploaded to the FPGA prototyping board. The whole process of synthesizing and implementing the design is subdivided into several steps, that can be seen, if you click on the plus sign in the processes sub window. After the completion of each step an update of the FPGA Design Summary will be shown in the corresponding sub window in the upper right corner. For example the device utilization (i.e. the size of your CPU plus the framework) will be shown for the different types of elementary hardware available on the FPGA (e.g. clocks, logic, BRAMs). This is a first hint, how big your CPU actually is, but as it will be explained in Chapter 6.4 these values are not completely accurate, as they don’t include the plain CPU, but they also include the Framework, which consists of many different parts. - 57 -
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Laboratory: “Designing Applicatio
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6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19 and 20: Successful Successful dissolving di
Page 21 and 22: Instruction Description Instruction
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45 and 46: 5 ModelSim ModelSim is a full-featu
Page 47 and 48: 5.1.3 Compile the project Figure 5-
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55: If you don’t already have a proje
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
Page 73 and 74: of the makeCoSy script. If an error
Page 75 and 76: the automatically generated compile
Page 77 and 78: instruction, as different custom in
Page 79 and 80: Directive Explanation .restrict .ch
Page 81 and 82: Now we will demonstrate how you can
Page 83 and 84: the user changes the value of the b
Page 85 and 86: • Huge decrease of cycle count
Page 87 and 88: of instructions together it might t
Page 89 and 90: Table of Figures Figure 1-1 GPPs, A
Page 91: References [CES] Homepage of the Ch
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Script for Laboratory: Designing embedded ASIPs - CES

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