Script for Laboratory: Designing embedded ASIPs - CES

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Figure 5-1 Creating a ModelSim Project 5.1.2 Include the testbench and ASIP Meister CPU files Choose the icon Add Existing File. Browse to the meister/dlx_basis.syn directory of your ASIP Meister project. Here you will find the VHDL files for synthesis. There is also a VHDL model of the processor in the .sim directory, but don’t use the files of the .sim directory, as they don’t work properly. Mark all the files and confirm the dialog with open. Once again, choose the icon Add Existing File to add the testbench file tb_ASIPmeister.vhd in the ModelSim directory of your current project. - 46 -
5.1.3 Compile the project Figure 5-2 Adding files to a ModelSim Project Menu: Compile > Compile Order > Auto Generate Every file gets compiled and you can see the result of the compile process. ModelSim determines automatically the compile order of the VHDL files. After closing the dialog every file should have a green mark behind its name, showing that the compilation was successful (instead of the question marks, shown in Figure 5-3. A green mark with a yellow dot is a warning that usually is a problem. So take care about the warnings. IMPORTANT: When you edit your CPU in ASIP Meister and execute HDL Generation, then the VHDL files are regenerated and have to be recompiled. ASIP Meister might even generate new files, that haven’t been there in the previous set of VHDL files, e.g. for new pipeline registers that are needed for modified MicroOp Descriptions. These new VHDL files are not included into your ModelSim project yet. Also previously needed VHDL files might no longer be needed for a modified ASIP Meister CPU and ModelSim will complain about these files while recompiling. To avoid manually checking every VHDL file, whether it already was included into your project or whether it is a new file, you can do the following: Delete the meister/dlx_basis.syn directory before executing the HDL Generation; this will make sure, that no files are existing, that are no longer needed. Remove all ASIP Meister VHDL files out of your ModelSim project and after executing the HDL Generation just add the new created VHDL files from the meister/dlx_basis.syn directory, like explained in the previous point. - 47 -
Page 1 and 2: Laboratory: “Designing Applicatio
Page 3 and 4: 6 Validating the CPU in Prototyping
Page 5 and 6: Figure 1-1 GPPs, ASIPs and ASICs [H
Page 7 and 8: • Command line interpreter Intera
Page 9 and 10: i. Copying files: the cp command co
Page 11 and 12: . Copying via ssh: Not all machines
Page 13 and 14: dlx_basis Applications ModelSim mei
Page 15 and 16: makeCoSy contCoSy Filename Explanat
Page 17 and 18: 3 Dlxsim Dlxsim [DLX-Package] is an
Page 19 and 20: Successful Successful dissolving di
Page 21 and 22: Instruction Description Instruction
Page 23 and 24: Option Description -dbb# (Debug Bas
Page 25 and 26: Instruction Format Parameters NO_AR
Page 27 and 28: Command Description stop {options}
Page 29 and 30: 3.3.2 Debugging with dlxsim This ch
Page 31 and 32: addComment1(); functionY(); addComm
Page 33 and 34: • If you manually want to write a
Page 35 and 36: 4.3 Tutorial for the “Flexible Ha
Page 37 and 38: in direction; The in keyword means
Page 39 and 40: amount : in std_logic_vector(7 down
Page 41 and 42: Add the three signals to the contro
Page 43 and 44: data_in : in std_logic_vector($W1 d
Page 45: 5 ModelSim ModelSim is a full-featu
Page 49 and 50: Mark the wave.do file in your Model
Page 51 and 52: Figure 5-6 ModelSim waves Signal Ex
Page 53 and 54: • Always invoke ModelSim in the s
Page 55 and 56: If you don’t already have a proje
Page 57 and 58: CPU VHDL Files have been generated
Page 59 and 60: After the TestData-files for your a
Page 61 and 62: However, you can’t force the synt
Page 63 and 64: Timing (Timing Analyzer)” will op
Page 65 and 66: 7 Power estimation In this tutorial
Page 67 and 68: - Start the simulation (Simulate/ s
Page 69 and 70: 8 CoSy compiler The CoSy compiler d
Page 71 and 72: When you manually have to fix some
Page 73 and 74: of the makeCoSy script. If an error
Page 75 and 76: the automatically generated compile
Page 77 and 78: instruction, as different custom in
Page 79 and 80: Directive Explanation .restrict .ch
Page 81 and 82: Now we will demonstrate how you can
Page 83 and 84: the user changes the value of the b
Page 85 and 86: • Huge decrease of cycle count
Page 87 and 88: of instructions together it might t
Page 89 and 90: Table of Figures Figure 1-1 GPPs, A
Page 91: References [CES] Homepage of the Ch

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