Data Sheet - Freescale Semiconductor

3.1.22 DSI3 Communication CRC Polynomial registers
The DSI3 communication CRC polynomial registers are user programmed read/write registers which contain the CRC
polynomials used for communication. The register is included in the read/write array verification described in Section 3.2.
Table 27. DSI3 Communication CRC Polynomial registers
Location Bit
Address Register 7 6 5 4 3 2 1 0
$25 C_CRMCRCPLY C_CRMCRCPLY[7] C_CRMCRCPLY[6] C_CRMCRCPLY[5] C_CRMCRCPLY[4] C_CRMCRCPLY[3] C_CRMCRCPLY[2] C_CRMCRCPLY[1] C_CRMCRCPLY[0]
$26 R_CRMCRCPLY R_CRMCRCPLY[7] R_CRMCRCPLY[6] R_CRMCRCPLY[5] R_CRMCRCPLY[4] R_CRMCRCPLY[3] R_CRMCRCPLY[2] R_CRMCRCPLY[1] R_CRMCRCPLY[0]
$27 PDCMCRCPLY PDCMCRCPLY[7] PDCMCRCPLY[6] PDCMCRCPLY[5] PDCMCRCPLY[4] PDCMCRCPLY[3] PDCMCRCPLY[2] PDCMCRCPLY[1] PDCMCRCPLY[0]
Factory Default 0 0 1 0 1 1 1 1
The C_CRMCRCPLY register contains the 8-bit CRC polynomial used for the Command and Response Mode command as well
as the Background Diagnostic Mode command. The default polynomial is x 8 + x 5 + x 3 + x 2 + x + 1. When this register value is
changed using a Command and Response Mode Register Write command, the new polynomial value is enabled for the next
Command and Response Mode command received.
The R_CRMCRCPLY register contains the 8-bit CRC polynomial used for the Command and Response Mode response as well
as the Background Diagnostic Mode response. The default polynomial is x 8 + x 5 + x 3 + x 2 + x + 1. When this register value is
changed using a Command and Response Mode Register Write command, the new polynomial value is enabled for the response
to the next Command and Response Mode command received. The response to the Register Write command uses the original
polynomial value.
The PDCMCRCPLY register contains the 8-bit CRC polynomial used for the Periodic Data Collection Mode response. The default
polynomial is x 8 + x 5 + x 3 + x 2 + x + 1. This polynomial is enabled once the device enters Periodic Data Collection Mode as
described in Section 4.3.
3.1.23 Acceleration Factory Configuration register (ACC_FCTCFG)
The Acceleration Factory Configuration register is a factory-programmable OTP register which contains acceleration data
specific configuration information. The register is included in the factory-programmed OTP verification. Reference Section 3.2 for
details regarding the OTP verification.
Table 28. Acceleration Factory Configuration register (ACC_FCTCFG)
Location Bit
Address Register 7 6 5 4 3 2 1 0
$30 ACC_FCTCFG 0 PCM AXIS RNG[4] RNG[3] RNG[2] RNG[1] RNG[0]
Factory Default 0 0 0 0 0 0 0 0
3.1.23.1 PCM Enable Bit (PCM)
The PCM bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a pulse code
modulated signal proportional to the acceleration response. Reference Section 3.5.4.10 for more information regarding the PCM
output. When the PCM bit is cleared, the PCM output pin is actively pulled low.
PCM PCM Output
0 Actively pulled low
1 PCM signal enabled
3.1.23.2 Axis Indication Bit (AXIS)
The axis indication bit indicates the axes of sensitivity as shown below.
AXIS Axis
0 X
1 Z
MMA27XXW
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