Data Sheet - Freescale Semiconductor

3.4 Internal oscillator
The device includes a factory-trimmed oscillator as specified in Section 2.8.
3.4.1 Oscillator training
The device includes a feature to train the oscillator to a tighter accuracy than the factory-trimmed capability assuming the system
master has a tighter oscillator accuracy than the slave factory trimmed capability. Oscillator training is enabled if the CK_CAL_EN
bit is set in the CRM_CFG register and is accomplished by verifying the timing of periodic transmissions from the master against
the values stored in the CRM_PER[1:0] and PDCM_PER[2:0] bits of the user read/write register array. The master programs the
intended Periodic Data Collection Mode command period into the PDCM_PER[2:0] bits and the intended Command and
Response Mode command period into the CRM_PER[1:0] bits. The device then calculates the number of transmission periods
for every 4 ms (n CRM_PER_4ms_TYP and n PDCM_PER_4ms_TYP ).
In Command and Response Mode, oscillator training is completed over 4 ms periods if and only if the CK_CAL_EN bit is set and
the Command and Response Mode period is between 500 μs and 4 ms, inclusive. The following procedure is used to train the
oscillator (Figure 11):
1. The device counts the number of oscillator cycles in nCRM_PER_4ms_TYP periods (nOSC_4ms ).
2. nOSC_4ms is compared to nOSC_4ms_TYP . If the value is within the acceptable training window (OscTrainWIN ) specified in
Section 2.8, an oscillator adjustment is made. Otherwise, no adjustment is made.
a) If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ , the oscillator frequency target is decreased by
OscTrainRES .
b) If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ , the oscillator frequency target is increased by OscTrainRES .
c) The oscillator frequency target value is changed at the end of the command blocking time for the command ending
the nCRM_PER_OSC calculation.
If the CK_CAL_EN bit is cleared after oscillator training has already been initiated, the state of the oscillator is determined by the
state of the CK_CAL_RST bit in the CRM_CFG register. If the CK_CAL_RST bit is cleared, the last adjustment value for the
oscillator is maintained. If the CK_CAL_RST bit is set, the oscillator is reset to its untrained value with the untrained tolerance
specified in Section 2.8.
Command
Response
One CRM Period
4ms = nCRM_PER_4ms_TYP nOSC_4ms t CmdBlock_CRM
Oscillator
Adjustment
Figure 11. Command and Response Mode oscillator training timing diagram
New Oscillator
Count Starts
In Periodic Data Collection Mode, oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is set. The following
procedure is used to train the oscillator (reference Figure 12):
1. The device counts the number of oscillator cycles in nPDCM_PER_4ms_TYP periods (nOSC_4ms ).
2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training window (OscTrainWIN) specified in
Section 2.8, an oscillator adjustment is made. Otherwise, no adjustment is made.
a) If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency target is decreased by
OscTrainRES .
b) If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target is increased by OscTrainRES. c) The oscillator frequency target value is changed at the end of the command blocking time for the command ending
the nPDCM_PER_OSC calculation.
MMA27XXW
Sensors
Freescale Semiconductor, Inc. 37
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