Data Sheet - Freescale Semiconductor

3.6 DSI3 physical layer
3.6.1 Command receiver
The command receive block converts voltage transitions on the BUS_I pin to a digital pulse train for decoding by the DSI data
link layer.
The supply voltage can vary throughout the specified range, so the communication high voltage (V HIGH) must be sampled and
averaged with a low-pass filter. The communication low voltage is then determined by comparing the supply voltage to the
sampled and averaged V HIGH voltage. Figure 28 shows a block diagram of the command receiver physical layer.
BUS_I
V SS
V DELTA_THRESH
+ -
VHigh_Sample
Cmd_Block
V HIGH
Command_Detect
Figure 28. Command receiver physical layer
The start of a command is detected when the comparator output (Command_Detect) is low. The comparator output is input to a
counter that is updated at the internal oscillator frequency. Control logic monitors the counter output and generates the following
signals:
1. Cmd_Start
a) Asserted when the counter reaches a value of one.
b) Deasserted at POR, if the counter does not reach Cmd_Valid_Count (tCmd_Valid) within tCmd_BitTime of Cmd_Start
assertion, or at the end of the command blocking time for the operating mode (tCmdBlock_DISC, tCmdBlock_CRM ,
tCmdBlock_PDCM , tCmdBlock_BDM ).
2. Cmd_Valid
a) Asserted if the counter reaches Cmd_Valid_Count within tCMD_BitTime of Cmd_Start assertion (tCmd_Valid). b) Deasserted at POR and when Cmd_Start is deasserted.
3. VHigh_Sample
a) Asserted tDSI_DISC_POR after POR and when Cmd_Start is deasserted.
b) Deasserted when Cmd_Start is asserted.
4. Cmd_Block:
a) Asserted based on the operating mode:
– Discovery Mode: A complete command is received as defined in Section 4.1.3 and Section 2.6.
– Command and Response Mode: A complete command is received as defined in Section 4.2 and Section 2.6.
– Periodic Data Collection Mode: A complete command is received as defined in Section 4.3 and Section 2.6.
b) Deasserted at POR and when Cmd_Start is deasserted.
Once a full command is received, based on the operating mode, the command is transferred to the DSI data link layer for
decoding.
f OSC
Cmd_Block
VHigh_Sample
Figure 29 shows a timing diagram of the command receiver when a valid command is received, and Figure 30 shows a timing
diagram of the command receiver when a microcut is received during the command window. Voltage values and timing
parameters are specified in Section 2.3 and Section 2.7.
MMA27XXW
Sensors
Freescale Semiconductor, Inc. 55
D
R
Counter
Count
Command_Detect
Control
Logic
Command
Cmd_Start
Cmd_Valid