Data Sheet - Freescale Semiconductor

4.4 Maximum number of devices on a network
The theoretical maximum number of devices on a DSI3 network is 16: 1 master and 15 slaves. The practical limit for the number
of devices on a bus is dependent on the minimum common capability of the devices on the bus. The capability of the device is
different depending on the bus configuration and operating mode. The impact of the device capability on the practical limit for the
number of devices on the network is described in this section.
4.4.1 Preconfigured, Parallel Connected Network
The number of devices in a preconfigured, parallel connected network is not directly limited by the capability of the device. The
practical limit is determined by a combination of the following:
• The capability of the master device, including, but not limited to:
— The bus operating voltage
— The bus supply current
— The bus current limit
— The bit rate
— The response current detection capability (distinguishing response current from quiescent current)
• The total quiescent current of all slaves on the network.
4.4.2 Bus switch connected daisy-chain network
The number of devices in a bus switch connected daisy-chain network is not directly limited by the capability of the device. The
practical limit is determined by a combination of the following:
• The capability of the master device, including, but not limited to:
— The bus operating voltage
— The bus supply current
— The bus current limit
— The bit rate
— The response current detection capability (distinguishing response current from quiescent current)
• The total quiescent current of all slaves on the network.
• The current handling capability and resulting voltage drop of the external bus switches in the network.
4.4.3 Resistor connected daisy-chain network using Discovery Mode
The number of devices in a resistor connected daisy-chain network is limited by the capability of the device. The maximum
number of equivalent devices connected to the BUS_O pin of the device is three. This is limited by the total quiescent current
drawn from the BUS_O pin during Discovery Mode (I BUS_O_q).
The practical limit is determined by a combination of the above restriction and the following:
• The capability of the master device, including, but not limited to:
— The bus operating voltage
— The bus supply current
— The bus current limit
— The bit rate
— The response current detection capability (distinguishing response current from quiescent current)
• The total quiescent current of all slaves on the network.
• The maximum allowed quiescent current drawn from the BUS_O pin of other slaves in the system.
• The resulting voltage drop of the Discovery Mode resistors in all slaves in the network.
MMA27XXW
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Freescale Semiconductor, Inc. 77