Data Sheet - Freescale Semiconductor

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3.6.4 Bus-switch control The bus-switch output pin is the driver for a high-side, daisy-chain switch. When switch connected daisy-chain mode is used, as described in Section 4.1.2, the BUSSW pin is connected to the gate of an external p-channel FET which connects BUS_I to the next slave in the daisy chain. If used, an external pullup resistor is required on the gate of the p-channel FET. Reference Figure 3 on page 5 for details on the recommended external circuitry. Bus Switch Enable 3.7 Data transmission modes 3.7.1 Simultaneous Sampling mode MMA27XXW Figure 34. Daisy-chain bus switch driver block diagram Figure 35. Simultaneous Sampling mode Sensors 58 Freescale Semiconductor, Inc. R1 BUSIN M1 To Next Device on the Chain
3.7.2 Synchronous Sampling mode with minimum latency 3.8 Initialization timing POR t DSP_POR POR Internal Delay t DSI_POR t OCPH1 Figure 36. Synchronous sampling mode with minimum latency Offset Cancellation Offset Cancellation Phase 1 Phase 2 Discovery Mode t OCPH2 Offset Cancellation Normal User set up and self-test control through CRM Read Status Registers (DEVSTAT, DEVSTAT2) Initialize Signal Chain Initialize Communication Offset Verification Self-test Verification t START_DISC Figure 37. Initialization timing Enabled/Disabled By OCFILT[2:0] Offset Verification Enter PDCM Command Periodic Data Collection Mode MMA27XXW Sensors Freescale Semiconductor, Inc. 59
Page 1 and 2:
Freescale Semiconductor Document Nu
Page 3 and 4:
1 Block Diagram, Pin Descriptions,
Page 5 and 6:
1.3 Application diagram C2 C3 C4 Ta
Page 7 and 8: 2 Electrical Characteristics 2.1 Ma
Page 9 and 10: 2.4 Electrical Characteristics - se
Page 11 and 12: 2.6 Dynamic electrical characterist
Page 13 and 14: 2.8 Dynamic electrical characterist
Page 15 and 16: 3.1.1 IC Type register The IC Type
Page 17 and 18: 3.1.9 Device Serial Number register
Page 19 and 20: 3.1.13.3 Clock Calibration Enable (
Page 21 and 22: 3.1.15.4 Periodic Data Collection M
Page 23 and 24: 3.1.19.2 Oscillator Training Error
Page 25 and 26: 3.1.19.14 BUS IN Undervoltage Error
Page 27 and 28: 3.1.22 DSI3 Communication CRC Polyn
Page 29 and 30: 3.1.25.1 Low-pass filter selection
Page 31 and 32: 3.1.28 Reserved Registers A registe
Page 33 and 34: 3.3 Voltage regulators The device d
Page 35 and 36: BUS_I V BUF V REG V REGA I DATA POR
Page 37 and 38: 3.4 Internal oscillator The device
Page 39 and 40: 3.5.2 Self-test interface The self-
Page 41 and 42: 3.5.4.1 Decimation Sinc filter The
Page 43 and 44: Figure 17. Low-pass filter characte
Page 49 and 50: 3.5.4.4 Signal compensation The dev
Page 51 and 52: Figure 24. 10 Hz offset cancellatio
Page 53 and 54: Figure 26. 0.1 Hz offset cancellati
Page 55 and 56: 3.6 DSI3 physical layer 3.6.1 Comma
Page 57: 3.6.2 Response transmitter The resp
Page 61 and 62: 4 DSI3 Protocol The DSI3 standard d
Page 63 and 64: 4.2.1.1 Bit encoding Figure 41 show
Page 65 and 66: 4.2.2.1 Symbol Encoding The device
Page 67 and 68: 4.2.3 DSI3 Command and Response Mod
Page 69 and 70: 4.2.4.2 Register Write Command The
Page 71 and 72: 4.2.4.4 Enter Periodic Data Collect
Page 73 and 74: 4.3.2 DSI3 Periodic Data Collection
Page 75 and 76: 4.3.3 DSI3 Periodic Data Collection
Page 77 and 78: 4.4 Maximum number of devices on a
Page 79 and 80: 6 Recommended Footprint Reference F
Page 81 and 82: CASE 2086-01 ISSUE C 16 LEAD QFN MM
Page 83 and 84: 8 Revision History Table 69. Revisi
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Data Sheet - Freescale Semiconductor

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