Data Sheet - Freescale Semiconductor

3.1.28 Reserved Registers
A register read command to a reserved register or a register with reserved bits will result in a valid response. The data for
reserved bits may be ‘0’ or ‘1’.
A register write command to a reserved register or a register with reserved bits will execute and result in a valid response. The
data for the reserved bits may be ‘0’ or ‘1’. A write to the reserved bits must always be ‘0’ for normal device operation and
performance.
3.1.29 Invalid Register Addresses
A register read command to a register address outside of the addresses listed in Table 4 will result in a valid response. The data
for the registers will be ‘0x00’.
A register write command to a register address outside of the addresses listed in Table 4 will not execute, but will result in a valid
response. The data for the registers will be ‘0x00’.
A register write command to a read-only register will not execute, but will result in a valid response. The data for the registers will
be the current contents of the register.
3.2 OTP and Read/Write register array CRC verification
3.2.1 Factory-programmed OTP array lock and verification
The factory-programmed OTP array is verified for errors with an error detection algorithm. The error verification is enabled only
when the factory-programmed array is locked.
Once enabled, the verification is continuously calculated on all bits in the registers listed below as well as on the factoryprogrammable
device configuration bits with the exception of the factory lock bit. If an error is detected in the OTP array, the
F_OTP_ERR is set in the DEVSTAT2 register.
Register Address Register Name
$09 PN
$0A - $0D SN0, SN1, SN2, SN3
$30 ACC_FCTCFG
$31 ACC_STDATA
The verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
3.2.2 User Programmable OTP Array Lock and Error Verification
The User Programmable OTP array is independently verified for errors with an error detection algorithm. The verification is
enabled only when the User Programmable OTP array is locked.
Once the LOCK_U bit is active, the verification is continuously calculated on the user programmable OTP Array, which includes
the registers listed below. If an error is detected in the OTP array, the U_OTP_ERR is set in the DEVSTAT2 register.
Register Address Register Name Number of Bits
$03 - $05 MODTYPE[2:0], MODMFGID[2:0], MODREV[2:0] 9
$06 USERID[7:0] 8
$11 PHYSADDR[3:0] 4
$20 DEVLOCK[7] 1
The verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
MMA27XXW
Sensors
Freescale Semiconductor, Inc. 31