Data Sheet - Freescale Semiconductor

Command
Response
MMA27XXW
Figure 12. Periodic Data Collection Mode oscillator training timing diagram
3.4.2 Oscillator training error handling
If oscillator training is enabled by the user, but the conditions are not correct to complete oscillator training, the OSC_TRAIN bit
is set in the DEVSTAT register. The following conditions will result in the OSCTRAIN_ERR bit being set.
• The CLK_CAL_EN bit in the CRM_CFG register is set, the device is in Command and Response Mode and Command and
Response Mode period is not set to 500 μs, 666 μs, 1000 μs, 1333 μs, 2000 μs or 4000 μs.
• The CLK_CAL_EN bit in the CRM_CFG register is set and the measured period (n OSC_4ms ) for either Command and
Response Mode or Periodic Data Collection Mode is outside of the Oscillator Training Window (OscTrain WIN ).
— The result of the comparison is filtered with an up and down counter.
— If nOSC_4ms is outside the oscillator training window, the counter is incremented.
— If nOSC_4ms is inside the oscillator training window, the counter is decremented.
— If the counter reaches 64 counts, the OSCTRAIN_ERR bit is set.
— The up and down counter has a maximum value of 127 and a minimum value of 0.
3.5 Acceleration signal path
3.5.1 Transducer
One PDCM Period
4ms = nPDCM_PER_4ms_TYP nOSC_4ms The device transducer is an overdamped mass-spring-damper system defined by the following transfer function:
Hs ( )
where:
ζ = Damping Ratio
ωn = Natural Frequency = 2∗Π∗fn Reference Section 2.7 for transducer parameters.
=
2
ω
n
s 2
------------------------------------------------------
2
+ 2 ⋅ ξ ⋅ ω
n
⋅ s + ω
n
t CmdBlock_PDCM
Oscillator
Adjustment
New Oscillator
Count Starts
Eqn. 1
Sensors
38 Freescale Semiconductor, Inc.
t