Data Sheet - Freescale Semiconductor

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3.2.3 User Programmable Read/Write Array Lock and CRC Verification The User Programmable read/write array is independently verified for errors with an error detection algorithm. The verification is enabled only when the PDCM_EN bit is set in the PDCM_EN register. Once the PDCM_EN bit is set, register writes are ignored and the verification is continuously calculated on the user programmable read/write array, which includes the registers listed below. If an error is detected in the array, the U_RW_ERR is set in the DEVSTAT2 register. Register Address Register Name $11 PHYSADDR[3:0] - Secondary Register written during Discovery Mode and/or CRM $12 - $1E BDM_CFG, CRM_CFG, PDCM_CFG, PDCM_EN, CHIPTIME, PDCM_PER_L, PDCM_PER_H, PDCM_RSPST_L, PDCM_RSPST_H, PDCM_CMD_B_L, PDCM_CMD_B_H, SOURCEID, BUSSW_CTRL $23 ST_CONTROL $24 WRITE_NVM_EN $25 - $27 C_CRMCRCPLY, R_CRMCRCPLY, PDCMCRCPLY $32 ACC_CFG MMA27XXW Sensors 32 Freescale Semiconductor, Inc.
3.3 Voltage regulators The device derives its internal supply voltage from the BUS_I and V SS pins. The internal regulators are supplied by a buffer regulator (V BUF) to provide immunity from EMC and supply dropouts on BUS_I. External filter capacitors are required, as shown in Figure 3 on page 5. The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the internal voltages have increased above the undervoltage detection thresholds. The voltage monitor asserts internal reset when the external supply or internally regulated voltages fall below the undervoltage detection thresholds. A reference generator provides a reference voltage for the ΣΔ converter. BUS_I V REF Bandgap Reference Trim Voltage Regulator V REGA V REF V REF BUS_I V BUF V REG VREGA VREF V BUF Voltage Regulator V BUF Trim Voltage Regulator Figure 6. Voltage regulation and monitoring 3.3.1 V BUF , V REG and V REGA regulator capacitor Reference Generator Comparator Comparator Comparator Comparator Bias Generator V REGA Oscillator ΣΔ Converter OTP Array Digital Logic V REGA The internal regulators require an external capacitor between the V BUF pin and the V SS pin, the V REG pin and the V SS pin and the V REGA pin and the V SSA pin for stability. Figure 3 on page 5 shows the recommended types and values for each of these capacitors. MMA27XXW Sensors Freescale Semiconductor, Inc. 33 V REG Trim V REF_MOD Trim DSP BUSI_UV_ERR VBUF_UV_ERR POR V BUF V REG
Page 1 and 2: Freescale Semiconductor Document Nu
Page 3 and 4: 1 Block Diagram, Pin Descriptions,
Page 5 and 6: 1.3 Application diagram C2 C3 C4 Ta
Page 7 and 8: 2 Electrical Characteristics 2.1 Ma
Page 9 and 10: 2.4 Electrical Characteristics - se
Page 11 and 12: 2.6 Dynamic electrical characterist
Page 13 and 14: 2.8 Dynamic electrical characterist
Page 15 and 16: 3.1.1 IC Type register The IC Type
Page 17 and 18: 3.1.9 Device Serial Number register
Page 19 and 20: 3.1.13.3 Clock Calibration Enable (
Page 21 and 22: 3.1.15.4 Periodic Data Collection M
Page 23 and 24: 3.1.19.2 Oscillator Training Error
Page 25 and 26: 3.1.19.14 BUS IN Undervoltage Error
Page 27 and 28: 3.1.22 DSI3 Communication CRC Polyn
Page 29 and 30: 3.1.25.1 Low-pass filter selection
Page 31: 3.1.28 Reserved Registers A registe
Page 35 and 36: BUS_I V BUF V REG V REGA I DATA POR
Page 37 and 38: 3.4 Internal oscillator The device
Page 39 and 40: 3.5.2 Self-test interface The self-
Page 41 and 42: 3.5.4.1 Decimation Sinc filter The
Page 43 and 44: Figure 17. Low-pass filter characte
Page 49 and 50: 3.5.4.4 Signal compensation The dev
Page 51 and 52: Figure 24. 10 Hz offset cancellatio
Page 53 and 54: Figure 26. 0.1 Hz offset cancellati
Page 55 and 56: 3.6 DSI3 physical layer 3.6.1 Comma
Page 57 and 58: 3.6.2 Response transmitter The resp
Page 59 and 60: 3.7.2 Synchronous Sampling mode wit
Page 61 and 62: 4 DSI3 Protocol The DSI3 standard d
Page 63 and 64: 4.2.1.1 Bit encoding Figure 41 show
Page 65 and 66: 4.2.2.1 Symbol Encoding The device
Page 67 and 68: 4.2.3 DSI3 Command and Response Mod
Page 69 and 70: 4.2.4.2 Register Write Command The
Page 71 and 72: 4.2.4.4 Enter Periodic Data Collect
Page 73 and 74: 4.3.2 DSI3 Periodic Data Collection
Page 75 and 76: 4.3.3 DSI3 Periodic Data Collection
Page 77 and 78: 4.4 Maximum number of devices on a
Page 79 and 80: 6 Recommended Footprint Reference F
Page 81 and 82: CASE 2086-01 ISSUE C 16 LEAD QFN MM
Page 83 and 84:
8 Revision History Table 69. Revisi
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Data Sheet - Freescale Semiconductor

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