Data Sheet - Freescale Semiconductor

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1.2 Pin descriptions Table 1. Pin descriptions MMA27XXW Figure 2. Pin connections Pin Pin name Formal name Definition 1 BUS_O Supply out This pin is connected to the BUS_I pin through an internal sense resistor and provides the supply connection to the next slave in a daisy-chain configuration. An external capacitor must be connected between this pin and V SS. Reference Figure 3. 2 NC Not connected This pin is not internally connected and must be left unconnected or tied to V SS in the application. 3 BUS_I Supply and communication This pin is connected to the DSI supply line and supplies power to the device. An external capacitor must be connected between this pin and BUSRTN. Reference Figure 3. 4 BUSRTN Supply return This pin is the DSI supply return node. 5 PCM Pulse code modulated output 6 TEST_SCLK SPI clock 7 TEST_MISO SPI data out 8 TEST_MOSI SPI data in 9 V REG Internal supply 10 TEST_CS Chip select 11 V REGA 12 V SS Internal supply Internal supply return 13 V BUF Power supply BUS_O NC BUS_I BUSRTN 1 2 3 4 BUSSW PCM TEST TEST_SCLK TEST2 TEST_MISO If the PCM output is enabled, this pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. If PCM is unused, this pin must be left unconnected. This input pin provides the serial clock to the SPI port for test purposes. An internal pull-down device is connected to this pin. This pin must be grounded or left unconnected in the application. This pin functions as the serial data output from the SPI port for test purposes. This pin must be left unconnected in the application. This pin functions as the serial data input to the SPI port for test purposes. An internal pull-down device is connected to this pin. This pin must be grounded or left unconnected in the application. This pin is connected to the power supply for the internal circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 3. This input pin provides the chip select to the SPI port for test purposes. An internal pullup device is connected to this pin. This pin must be left unconnected in the application. This pin is connected to the power supply for the internal circuitry. An external capacitor must be connected between this pin and VSSA . Reference Figure 3. This pin is the power supply return node for the internal power supplies and must be connected to BUSRTN in this application. This pin is connected to a buffer regulator for the internal circuitry. The buffer regulator supplies the internal regulators to provide immunity from EMC and supply dropouts. An external capacitor must be connected between this pin and VSS . Reference Figure 3. 14 TEST2 Test pin This pin is must be connected to VSS in the application. 15 TEST Test pin This pin is must be connected to VSS in the application. This pin is the drive for a high-side, daisy-chain switch. When switch is connected, daisy-chain mode is 16 BUSSW Bus switch gate drive used, this pin is connected to the gate of a p-channel FET which connects BUS_I to the next slave in the daisy chain. An external pullup resistor is required on the gate of the p-channel FET. Reference Section 3.6.4. If unused, this pin must be left unconnected. 17 PAD Die attach pad This pin is the die attach flag, and is internally connected to VSS . Reference Section 6 for die attach pad connection details. Corner pads Corner pads The corner pads are internally connected to VSS. Sensors 4 Freescale Semiconductor, Inc. V BUF 16 15 14 13 17 5 6 7 8 TEST_MOSI 12 11 10 9 V SS VREGA TEST_CS V REG
1.3 Application diagram C2 C3 C4 Table 2. External component recommendations VBUF BUS_I VREG V REGA V SS BUSRTN BUS_O BUSSW BUS_I BUS_I Figure 3. MMA27XXW/17XXW application diagram Ref Des Type Description Purpose BUSIN EMC and ESD protection. Capacitor value is dependent C1 Ceramic 220 pF, 10%, 50 V minimum, X7R on the DSI3 master device and must be chosen by the system implementer. C2 Ceramic 1 μF, 10%, 10 V minimum, X7R Voltage regulator output capacitor C3 Ceramic 1 μF, 10%, 10 V minimum, X7R Voltage regulator output capacitor C4 Ceramic 1 μF, 10%, 10 V minimum, X7R Voltage regulator output capacitor C5 Ceramic 100 pF, 10%, 50 V minimum, X7R BUSOUT EMC and ESD protection C6 Ceramic 100 pF, 10%, 50 V minimum, X7R BUSOUT EMC and ESD protection R1 General purpose 100 kΩ, 5%, 200 PPM Pullup resistor for external high-side, daisy-chain FET M1 P-channel MOSFET High-side, daisy-chain transistor D1 Zener diode MMBZ27Vxxxx or equivalent ESD protection diode MMA27XXW Sensors Freescale Semiconductor, Inc. 5 C1 R1 Optional for Daisy Chain Optional for ESD D1 C5 C6 M1 BUSIN BUSRTN BUSOUT BUSOUT DC
Page 1 and 2: Freescale Semiconductor Document Nu
Page 3: 1 Block Diagram, Pin Descriptions,
Page 7 and 8: 2 Electrical Characteristics 2.1 Ma
Page 9 and 10: 2.4 Electrical Characteristics - se
Page 11 and 12: 2.6 Dynamic electrical characterist
Page 13 and 14: 2.8 Dynamic electrical characterist
Page 15 and 16: 3.1.1 IC Type register The IC Type
Page 17 and 18: 3.1.9 Device Serial Number register
Page 19 and 20: 3.1.13.3 Clock Calibration Enable (
Page 21 and 22: 3.1.15.4 Periodic Data Collection M
Page 23 and 24: 3.1.19.2 Oscillator Training Error
Page 25 and 26: 3.1.19.14 BUS IN Undervoltage Error
Page 27 and 28: 3.1.22 DSI3 Communication CRC Polyn
Page 29 and 30: 3.1.25.1 Low-pass filter selection
Page 31 and 32: 3.1.28 Reserved Registers A registe
Page 33 and 34: 3.3 Voltage regulators The device d
Page 35 and 36: BUS_I V BUF V REG V REGA I DATA POR
Page 37 and 38: 3.4 Internal oscillator The device
Page 39 and 40: 3.5.2 Self-test interface The self-
Page 41 and 42: 3.5.4.1 Decimation Sinc filter The
Page 43 and 44: Figure 17. Low-pass filter characte
Page 49 and 50: 3.5.4.4 Signal compensation The dev
Page 51 and 52: Figure 24. 10 Hz offset cancellatio
Page 53 and 54: Figure 26. 0.1 Hz offset cancellati
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3.6 DSI3 physical layer 3.6.1 Comma
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3.6.2 Response transmitter The resp
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3.7.2 Synchronous Sampling mode wit
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4 DSI3 Protocol The DSI3 standard d
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4.2.1.1 Bit encoding Figure 41 show
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4.2.2.1 Symbol Encoding The device
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4.2.3 DSI3 Command and Response Mod
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4.2.4.2 Register Write Command The
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4.2.4.4 Enter Periodic Data Collect
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4.3.2 DSI3 Periodic Data Collection
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4.3.3 DSI3 Periodic Data Collection
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4.4 Maximum number of devices on a
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6 Recommended Footprint Reference F
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CASE 2086-01 ISSUE C 16 LEAD QFN MM
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8 Revision History Table 69. Revisi
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Data Sheet - Freescale Semiconductor

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