Data Sheet - Freescale Semiconductor

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$Set of General Math and Motor Control Functions for ARM Cortex ...$

3.5.4.9 Output data values Table 37. Nominal acceleration data values Unsigned digital value 3.5.4.10 PCM output function The device provides the option for a PCM output function. The PCM output is enabled if the PCM bit is set in the ACC_FCTCFG register. Selecting the PCM output enables the following functions: • The acceleration value output from the offset cancellation block is saturated to 9-bits and converted to an unsigned value. • The 9-bit acceleration value is input into a summer clocked at 8MHz. • The carry from the summer circuit is output to the PCM pin. A block diagram of the PCM output is shown in Figure 27. MMA27XXW 16-bit data 10-bit data Nominal acceleration (g) Signed digital value Unsigned digital value Signed digital value Decimal Hex Decimal Hex Decimal Hex Decimal Hex 33280 to 65535 0x8200 to 0xFFFF 512 to 32767 0x200 to 0x7FFF 25 g range Figure 27. PCM output function block diagram 125 g range 187 g range NA NA NA NA Overrange data 250 g range 375 g range 33279 0x81FF 511 0x1FF 1023 0x3FF 511 0x1FF 24.9512 124.756 186.633 249.512 374.277 33278 0x81FE 510 0x1FE 1022 0x3FE 510 0x1FE 24.9023 124.512 186.267 249.023 373.544 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 32770 0x8002 2 0x0002 514 0x202 2 0x002 0.976563 0.488281 0.730460 0.976563 1.46488 32769 0x8001 1 0x0001 513 0x201 1 0x001 0.048828 0.244141 0.365230 0.488281 0.732440 32768 0x8000 0 0x0000 512 0x200 0 0x000 0 0 0 0 0 32767 0x7FFF -1 0xFFFF 511 0x1FF -1 0x3FF -0.048828 -0.24414 -0.365230 -0.488281 -0.732440 32766 0x7FFE -2 0xFFFE 510 0x1FE -2 0x3FE -0.976563 -0.488281 -0.730460 -0.976563 -1.46488 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 32258 0x7E02 -510 0xFE02 2 0x002 -510 0x202 -24.9023 -124.512 -186.267 -249.023 -373.544 32257 0x7E01 -511 0xFE01 1 0x001 -511 0x201 -24.9512 -124.756 -186.633 -249.512 -374.277 1 to 32256 0x0001 to 0x7E00 -32767 to -512 0x8001 to 0xFE00 NA NA NA NA Overrange Data 0 0x0000 -32768 0x8000 0 0x000 -512 0x200 Fault DSP Output 9 A B CARRY 9 Bit ADDER SUM f CLK 9 9 D Q D Q D Q D Q D Q D Q DFF Q DFF Q FF Q FF FF FF FF CLK FF CLK FF Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q Sensors 54 Freescale Semiconductor, Inc. PCM
3.6 DSI3 physical layer 3.6.1 Command receiver The command receive block converts voltage transitions on the BUS_I pin to a digital pulse train for decoding by the DSI data link layer. The supply voltage can vary throughout the specified range, so the communication high voltage (V HIGH) must be sampled and averaged with a low-pass filter. The communication low voltage is then determined by comparing the supply voltage to the sampled and averaged V HIGH voltage. Figure 28 shows a block diagram of the command receiver physical layer. BUS_I V SS V DELTA_THRESH + - VHigh_Sample Cmd_Block V HIGH Command_Detect Figure 28. Command receiver physical layer The start of a command is detected when the comparator output (Command_Detect) is low. The comparator output is input to a counter that is updated at the internal oscillator frequency. Control logic monitors the counter output and generates the following signals: 1. Cmd_Start a) Asserted when the counter reaches a value of one. b) Deasserted at POR, if the counter does not reach Cmd_Valid_Count (tCmd_Valid) within tCmd_BitTime of Cmd_Start assertion, or at the end of the command blocking time for the operating mode (tCmdBlock_DISC, tCmdBlock_CRM , tCmdBlock_PDCM , tCmdBlock_BDM ). 2. Cmd_Valid a) Asserted if the counter reaches Cmd_Valid_Count within tCMD_BitTime of Cmd_Start assertion (tCmd_Valid). b) Deasserted at POR and when Cmd_Start is deasserted. 3. VHigh_Sample a) Asserted tDSI_DISC_POR after POR and when Cmd_Start is deasserted. b) Deasserted when Cmd_Start is asserted. 4. Cmd_Block: a) Asserted based on the operating mode: – Discovery Mode: A complete command is received as defined in Section 4.1.3 and Section 2.6. – Command and Response Mode: A complete command is received as defined in Section 4.2 and Section 2.6. – Periodic Data Collection Mode: A complete command is received as defined in Section 4.3 and Section 2.6. b) Deasserted at POR and when Cmd_Start is deasserted. Once a full command is received, based on the operating mode, the command is transferred to the DSI data link layer for decoding. f OSC Cmd_Block VHigh_Sample Figure 29 shows a timing diagram of the command receiver when a valid command is received, and Figure 30 shows a timing diagram of the command receiver when a microcut is received during the command window. Voltage values and timing parameters are specified in Section 2.3 and Section 2.7. MMA27XXW Sensors Freescale Semiconductor, Inc. 55 D R Counter Count Command_Detect Control Logic Command Cmd_Start Cmd_Valid
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Freescale Semiconductor Document Nu
Page 3 and 4: 1 Block Diagram, Pin Descriptions,
Page 5 and 6: 1.3 Application diagram C2 C3 C4 Ta
Page 7 and 8: 2 Electrical Characteristics 2.1 Ma
Page 9 and 10: 2.4 Electrical Characteristics - se
Page 11 and 12: 2.6 Dynamic electrical characterist
Page 13 and 14: 2.8 Dynamic electrical characterist
Page 15 and 16: 3.1.1 IC Type register The IC Type
Page 17 and 18: 3.1.9 Device Serial Number register
Page 19 and 20: 3.1.13.3 Clock Calibration Enable (
Page 21 and 22: 3.1.15.4 Periodic Data Collection M
Page 23 and 24: 3.1.19.2 Oscillator Training Error
Page 25 and 26: 3.1.19.14 BUS IN Undervoltage Error
Page 27 and 28: 3.1.22 DSI3 Communication CRC Polyn
Page 29 and 30: 3.1.25.1 Low-pass filter selection
Page 31 and 32: 3.1.28 Reserved Registers A registe
Page 33 and 34: 3.3 Voltage regulators The device d
Page 35 and 36: BUS_I V BUF V REG V REGA I DATA POR
Page 37 and 38: 3.4 Internal oscillator The device
Page 39 and 40: 3.5.2 Self-test interface The self-
Page 41 and 42: 3.5.4.1 Decimation Sinc filter The
Page 43 and 44: Figure 17. Low-pass filter characte
Page 49 and 50: 3.5.4.4 Signal compensation The dev
Page 51 and 52: Figure 24. 10 Hz offset cancellatio
Page 53: Figure 26. 0.1 Hz offset cancellati
Page 57 and 58: 3.6.2 Response transmitter The resp
Page 59 and 60: 3.7.2 Synchronous Sampling mode wit
Page 61 and 62: 4 DSI3 Protocol The DSI3 standard d
Page 63 and 64: 4.2.1.1 Bit encoding Figure 41 show
Page 65 and 66: 4.2.2.1 Symbol Encoding The device
Page 67 and 68: 4.2.3 DSI3 Command and Response Mod
Page 69 and 70: 4.2.4.2 Register Write Command The
Page 71 and 72: 4.2.4.4 Enter Periodic Data Collect
Page 73 and 74: 4.3.2 DSI3 Periodic Data Collection
Page 75 and 76: 4.3.3 DSI3 Periodic Data Collection
Page 77 and 78: 4.4 Maximum number of devices on a
Page 79 and 80: 6 Recommended Footprint Reference F
Page 81 and 82: CASE 2086-01 ISSUE C 16 LEAD QFN MM
Page 83 and 84: 8 Revision History Table 69. Revisi
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Data Sheet - Freescale Semiconductor

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