Data Sheet - Freescale Semiconductor

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MMA27XXW Figure 22. Low-pass filter characteristics: f C = 1200 Hz, 4-Pole, t S = 16 μs Sensors 48 Freescale Semiconductor, Inc.
3.5.4.4 Signal compensation The device includes internal gain and compensation circuitry to compensate for sensor offset, sensitivity and non-linearity. 3.5.4.5 Offset cancellation The device provides an optional offset cancellation circuit to remove internal offset error. A block diagram of the offset cancellation is shown in Figure 23. INPUT DATA Input Data downsampled to 256 μs OFFSET CANCELLATION n n z 1 2 a 0 1 – + ( ⋅ ) d d z 1 2 1 – LOW-PASS FILTER ⋅ ------------------------------------ + ( ⋅ ) The transfer function for the offset LPF is: 0.5 Hz (Derived from fOSC) OFFMON NEG OFFMON POS HIGH-PASS FILTER DATAPATH OFFSET RATE LIMITED DATAPATH 2 kHz (Derived from fOSC) OFFSET RATE LIMITING INC/DEC UP/DOWN COUNTER Figure 23. Offset cancellation block diagram Response parameters are specified in Section 2 and the offset LPF coefficients are specified in Table 36. During start up, two phases of the offset LPF are used to allow for fast convergence of the internal offset error during initialization. The timing for the startup phases is shown in Table 35. The offset low-pass filter used in normal operation is selected by the OC_FILT[2:0] bits in the ACC_CFG register. Output rate limiting can be applied to the output of the offset low-pass filter. Rate limiting is also enabled by the OC_FILT[2:0] bits. If rate limiting is enabled, the offset cancellation output is updated by OFF Step LSB every t OffRate seconds. The offset cancellation circuit output value is frozen when self-test is active, even if the offset cancellation circuit is in a startup phase. The timers controlling the startup phase times listed in Table 35 are not frozen. To ensure proper offset cancellation startup, prior to activating self-test, the user should verify that the offset cancellation initialization is complete by monitoring the OC_INIT bit in the DEVSTAT register. Eqn. 6 MMA27XXW Sensors Freescale Semiconductor, Inc. 49 CLK OFFSET MONITOR no 1 no 2 z Hz ( ) ao 0 1 – + ( ⋅ ) do 1 do 2 z 1 – = ⋅ ------------------------------------------- + ( ⋅ ) OUT INC/DEC UP/DOWN COUNTER CLK OC_FILT[0] OUT OFFMON CNTLIMIT To Interpolation OFF_ERR
Page 1 and 2: Freescale Semiconductor Document Nu
Page 3 and 4: 1 Block Diagram, Pin Descriptions,
Page 5 and 6: 1.3 Application diagram C2 C3 C4 Ta
Page 7 and 8: 2 Electrical Characteristics 2.1 Ma
Page 9 and 10: 2.4 Electrical Characteristics - se
Page 11 and 12: 2.6 Dynamic electrical characterist
Page 13 and 14: 2.8 Dynamic electrical characterist
Page 15 and 16: 3.1.1 IC Type register The IC Type
Page 17 and 18: 3.1.9 Device Serial Number register
Page 19 and 20: 3.1.13.3 Clock Calibration Enable (
Page 21 and 22: 3.1.15.4 Periodic Data Collection M
Page 23 and 24: 3.1.19.2 Oscillator Training Error
Page 25 and 26: 3.1.19.14 BUS IN Undervoltage Error
Page 27 and 28: 3.1.22 DSI3 Communication CRC Polyn
Page 29 and 30: 3.1.25.1 Low-pass filter selection
Page 31 and 32: 3.1.28 Reserved Registers A registe
Page 33 and 34: 3.3 Voltage regulators The device d
Page 35 and 36: BUS_I V BUF V REG V REGA I DATA POR
Page 37 and 38: 3.4 Internal oscillator The device
Page 39 and 40: 3.5.2 Self-test interface The self-
Page 41 and 42: 3.5.4.1 Decimation Sinc filter The
Page 43 and 44: Figure 17. Low-pass filter characte
Page 45 and 46: Figure 19. Low-pass filter characte
Page 47: Figure 21. Low-pass filter characte
Page 51 and 52: Figure 24. 10 Hz offset cancellatio
Page 53 and 54: Figure 26. 0.1 Hz offset cancellati
Page 55 and 56: 3.6 DSI3 physical layer 3.6.1 Comma
Page 57 and 58: 3.6.2 Response transmitter The resp
Page 59 and 60: 3.7.2 Synchronous Sampling mode wit
Page 61 and 62: 4 DSI3 Protocol The DSI3 standard d
Page 63 and 64: 4.2.1.1 Bit encoding Figure 41 show
Page 65 and 66: 4.2.2.1 Symbol Encoding The device
Page 67 and 68: 4.2.3 DSI3 Command and Response Mod
Page 69 and 70: 4.2.4.2 Register Write Command The
Page 71 and 72: 4.2.4.4 Enter Periodic Data Collect
Page 73 and 74: 4.3.2 DSI3 Periodic Data Collection
Page 75 and 76: 4.3.3 DSI3 Periodic Data Collection
Page 77 and 78: 4.4 Maximum number of devices on a
Page 79 and 80: 6 Recommended Footprint Reference F
Page 81 and 82: CASE 2086-01 ISSUE C 16 LEAD QFN MM
Page 83 and 84: 8 Revision History Table 69. Revisi

Data Sheet - Freescale Semiconductor

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