Data Sheet - Freescale Semiconductor
Data Sheet - Freescale Semiconductor
Data Sheet - Freescale Semiconductor
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3.5.4.4 Signal compensation<br />
The device includes internal gain and compensation circuitry to compensate for sensor offset, sensitivity and non-linearity.<br />
3.5.4.5 Offset cancellation<br />
The device provides an optional offset cancellation circuit to remove internal offset error. A block diagram of the offset cancellation<br />
is shown in Figure 23.<br />
INPUT DATA<br />
Input <strong>Data</strong> downsampled to 256 μs<br />
OFFSET CANCELLATION<br />
n n z<br />
1 2<br />
a<br />
0<br />
1 – + ( ⋅ )<br />
d d z<br />
1 2 1 –<br />
LOW-PASS FILTER<br />
⋅ ------------------------------------<br />
+ ( ⋅ )<br />
The transfer function for the offset LPF is:<br />
0.5 Hz (Derived from fOSC)<br />
OFFMON NEG<br />
OFFMON POS<br />
HIGH-PASS FILTER DATAPATH<br />
OFFSET RATE LIMITED DATAPATH<br />
2 kHz (Derived from fOSC)<br />
OFFSET RATE LIMITING<br />
INC/DEC<br />
UP/DOWN<br />
COUNTER<br />
Figure 23. Offset cancellation block diagram<br />
Response parameters are specified in Section 2 and the offset LPF coefficients are specified in Table 36.<br />
During start up, two phases of the offset LPF are used to allow for fast convergence of the internal offset error during initialization.<br />
The timing for the startup phases is shown in Table 35.<br />
The offset low-pass filter used in normal operation is selected by the OC_FILT[2:0] bits in the ACC_CFG register. Output rate<br />
limiting can be applied to the output of the offset low-pass filter. Rate limiting is also enabled by the OC_FILT[2:0] bits. If rate<br />
limiting is enabled, the offset cancellation output is updated by OFF Step LSB every t OffRate seconds.<br />
The offset cancellation circuit output value is frozen when self-test is active, even if the offset cancellation circuit is in a startup<br />
phase. The timers controlling the startup phase times listed in Table 35 are not frozen. To ensure proper offset cancellation<br />
startup, prior to activating self-test, the user should verify that the offset cancellation initialization is complete by monitoring the<br />
OC_INIT bit in the DEVSTAT register.<br />
Eqn. 6<br />
MMA27XXW<br />
Sensors<br />
<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc. 49<br />
CLK<br />
OFFSET MONITOR<br />
no<br />
1<br />
no<br />
2<br />
z<br />
Hz ( ) ao<br />
0<br />
1 – + ( ⋅ )<br />
do<br />
1<br />
do<br />
2<br />
z 1 –<br />
=<br />
⋅ -------------------------------------------<br />
+ ( ⋅ )<br />
OUT<br />
INC/DEC<br />
UP/DOWN<br />
COUNTER<br />
CLK<br />
OC_FILT[0]<br />
OUT<br />
OFFMON CNTLIMIT<br />
To Interpolation<br />
OFF_ERR