Data Sheet - Freescale Semiconductor

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5 Exception Handling Table 68 summarizes the exception conditions detected by the device and the response for each exception. Table 68. Exception handling Condition Exception PDCM_EN Power On Reset V BUS_I Undervoltage V BUF Undervoltage V REG Undervoltage V REGA Undervoltage V BUF Capacitor Test Failure V REGCapacitor Test Failure V REGA Capacitor Test Failure OTP CRC Fault (Factory Array) OTP CRC Fault (User Array) User R/W Array CRC Fault Self-test Activated Self-test Never Activated after POR MMA27XXW N/A Power Applied Description Device Response N/A V BUS_I < V BUS_I_UV_F N/A V BUF < V BUF_UV_F N/A V REG < V REG_UV_F N/A V REGA < V REGA_UV_F N/A N/A N/A N/A N/A Error detected in factoryprogrammed OTP array. Error detected in User programmed OTP array and the LOCK_U bit is set. 0 N/A N/A 1 0 1 0 1 Error detected in user read write registers and the PDCM_EN bit is set. ST activated during initialization ST activated in Periodic Data Collection Mode In initialization, before Self-test In PDCM, Self-test incomplete • Reference Section 3.8. • ST_INCMPLT Bit Set, PDCM S[3:0] = ‘1000’. • Response Current Deactivated. • BUSI_UV_ERR set. • The device reacts to all DSI commands but no response current is activated. • Response Current Deactivated. • VBUF_UV_ERR set. • The device reacts to all DSI commands but no response current is activated. • The device is held in Reset. • No response to DSI commands. • If activated, BUSSW is deactivated within tBS_OFF. • The device must be re-initialized when VREG returns above VPORCREG_r . • The device is held in Reset. • No response to DSI commands. • If activated, BUSSW is deactivated within tBS_OFF . • The device must be re-initialized when VREGA returns above VPORCREGA_r . • The device is reset and will continue to be reset every tPOR_CAPTEST until the capacitor failure is removed. • No response to DSI commands. • If activated, BUSSW is deactivated within tBS_OFF . • The device must be re-initialized when the capacitor failure is removed. • The device is reset and will continue to be reset every tPOR_CAPTEST until the capacitor failure is removed. • No response to DSI commands. • If activated, BUSSW is deactivated within tBS_OFF . • The device must be re-initialized when the capacitor failure is removed. • The device is reset and will continue to be reset every tPOR_CAPTEST until the capacitor failure is removed. • No response to DSI commands. • If activated, BUSSW is deactivated within tBS_OFF . • The device must be re-initialized when the capacitor failure is removed. • Periodic Data Collection Mode response data set to error response. • PDCM S[3:0] = ‘0010’). • Periodic Data Collection Mode response data set to error response. • PDCM S[3:0] = ‘0011’). • Periodic Data Collection Mode response data set to error response. • PDCM S[3:0] = ‘0100’). • Internal self-test circuitry enabled. • Self-test Activation Incomplete status cleared. • Acceleration Data Registers (ACC_DATAL, ACC_DATAH) contain self-test active data. • Periodic Data Collection Mode acceleration response data normal. • Self-test Activation ignored. • Normal Responses to Command and Response Mode. • Periodic Data Collection Mode acceleration response data normal. • ST_INCMPLT bit set, PDCM S[3:0] = ‘1000’. Sensors 78 Freescale Semiconductor, Inc.
6 Recommended Footprint Reference Freescale Application Note AN3111, latest revision: http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf Reference Freescale Application Note AN4530, latest revision: http://www.freescale.com/files/sensors/doc/app_note/AN4530.pdf MMA27XXW Sensors Freescale Semiconductor, Inc. 79
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Freescale Semiconductor Document Nu
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1 Block Diagram, Pin Descriptions,
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1.3 Application diagram C2 C3 C4 Ta
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2 Electrical Characteristics 2.1 Ma
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2.4 Electrical Characteristics - se
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2.6 Dynamic electrical characterist
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2.8 Dynamic electrical characterist
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3.1.1 IC Type register The IC Type
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3.1.9 Device Serial Number register
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3.1.13.3 Clock Calibration Enable (
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3.1.15.4 Periodic Data Collection M
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3.1.19.2 Oscillator Training Error
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3.1.19.14 BUS IN Undervoltage Error
Page 27 and 28: 3.1.22 DSI3 Communication CRC Polyn
Page 29 and 30: 3.1.25.1 Low-pass filter selection
Page 31 and 32: 3.1.28 Reserved Registers A registe
Page 33 and 34: 3.3 Voltage regulators The device d
Page 35 and 36: BUS_I V BUF V REG V REGA I DATA POR
Page 37 and 38: 3.4 Internal oscillator The device
Page 39 and 40: 3.5.2 Self-test interface The self-
Page 41 and 42: 3.5.4.1 Decimation Sinc filter The
Page 43 and 44: Figure 17. Low-pass filter characte
Page 49 and 50: 3.5.4.4 Signal compensation The dev
Page 51 and 52: Figure 24. 10 Hz offset cancellatio
Page 53 and 54: Figure 26. 0.1 Hz offset cancellati
Page 55 and 56: 3.6 DSI3 physical layer 3.6.1 Comma
Page 57 and 58: 3.6.2 Response transmitter The resp
Page 59 and 60: 3.7.2 Synchronous Sampling mode wit
Page 61 and 62: 4 DSI3 Protocol The DSI3 standard d
Page 63 and 64: 4.2.1.1 Bit encoding Figure 41 show
Page 65 and 66: 4.2.2.1 Symbol Encoding The device
Page 67 and 68: 4.2.3 DSI3 Command and Response Mod
Page 69 and 70: 4.2.4.2 Register Write Command The
Page 71 and 72: 4.2.4.4 Enter Periodic Data Collect
Page 73 and 74: 4.3.2 DSI3 Periodic Data Collection
Page 75 and 76: 4.3.3 DSI3 Periodic Data Collection
Page 77: 4.4 Maximum number of devices on a
Page 81 and 82: CASE 2086-01 ISSUE C 16 LEAD QFN MM
Page 83 and 84: 8 Revision History Table 69. Revisi
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Data Sheet - Freescale Semiconductor

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