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Data Sheet - Freescale Semiconductor

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3.2.3 User Programmable Read/Write Array Lock and CRC Verification<br />

The User Programmable read/write array is independently verified for errors with an error detection algorithm. The verification is<br />

enabled only when the PDCM_EN bit is set in the PDCM_EN register.<br />

Once the PDCM_EN bit is set, register writes are ignored and the verification is continuously calculated on the user<br />

programmable read/write array, which includes the registers listed below. If an error is detected in the array, the U_RW_ERR is<br />

set in the DEVSTAT2 register.<br />

Register Address Register Name<br />

$11 PHYSADDR[3:0] - Secondary Register written during Discovery Mode and/or CRM<br />

$12 - $1E<br />

BDM_CFG, CRM_CFG, PDCM_CFG, PDCM_EN, CHIPTIME, PDCM_PER_L, PDCM_PER_H, PDCM_RSPST_L,<br />

PDCM_RSPST_H, PDCM_CMD_B_L, PDCM_CMD_B_H, SOURCEID, BUSSW_CTRL<br />

$23 ST_CONTROL<br />

$24 WRITE_NVM_EN<br />

$25 - $27 C_CRMCRCPLY, R_CRMCRCPLY, PDCMCRCPLY<br />

$32 ACC_CFG<br />

MMA27XXW<br />

Sensors<br />

32 <strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.

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