Data Sheet - Freescale Semiconductor
Data Sheet - Freescale Semiconductor
Data Sheet - Freescale Semiconductor
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4.3.3 DSI3 Periodic <strong>Data</strong> Collection Mode timing<br />
A timing diagram for Periodic <strong>Data</strong> Collection Mode is shown in Figure 46. Timing parameters are specified in Section 2.7.<br />
BUS_I<br />
Response<br />
Current<br />
I q<br />
CMD_Start<br />
I q+ 2 x I RESP<br />
I q + I RESP<br />
t CMD_BitTime<br />
Figure 46. Periodic <strong>Data</strong> Collection Mode Timing Diagram<br />
4.3.4 Background Diagnostic Mode Response Transmission<br />
4.3.4.1 Symbol Encoding<br />
The Background Diagnostic Mode response symbol encoding is the same as the symbol encoding used for Command and<br />
Response Mode responses and is described in Section 4.2.2.1.<br />
4.3.4.2 Response Message Format<br />
The Background Diagnostic Mode response message format is the same as the format used for Command and Response Mode<br />
responses and is described in Section 4.2.2.1.<br />
• If a complete 32-bit command is received and decoded to a valid Command and Response Mode command the device<br />
provides a Background Diagnostic Mode response.<br />
• Responses are initiated by the master transmitting 1 bit Broadcast Read Commands following a completed Background<br />
Diagnostic Mode command transmission.<br />
• Responses are transmitted in one symbol fragments following the 1-bit Broadcast Read Command, using the same timing<br />
window within the frame that the Background Diagnostic Mode Command used.<br />
• Responses are transmitted if and only if Broadcast Read Commands are received.<br />
• Eight consecutive Broadcast Read Commands are required following a valid Background Diagnostic Mode command to<br />
complete a response transmission.<br />
• If any command other than the Broadcast Read Command is received, no response is transmitted and the remainder of the<br />
Broadcast Read Command response is terminated.<br />
• The data to be transmitted in the response is latched just before the first symbol of the Background Diagnostic Mode<br />
response.<br />
Reference Figure 47 for Background Diagnostic Mode timing.<br />
t START_PDCM<br />
1st Symbol 24th symbol<br />
t SLEW1_RESP t SLEW2_RESP<br />
t CHIP_PDCM<br />
t PER_PDCM<br />
4.3.4.3 Error Checking<br />
The error checking for Background Diagnostic Mode responses is the same as used for Command and Response Mode, and<br />
described in Section 4.2.1.3.<br />
MMA27XXW<br />
Sensors<br />
<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc. 75
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