Data Sheet - Freescale Semiconductor

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3.3.2 BUS_I, V BUF , V REG , V REGA , undervoltage monitor A circuit is incorporated to monitor the BUS_I supply voltage and the internally regulated voltages, V BUF, V REG and V REGA. If any of the voltages fall below the specified undervoltage thresholds in Section 2.3, the device will be react as listed below. • BUS_I MMA27XXW — If BUS_I falls below the specified threshold at any time, the BUSI_UV_ERR bit is set in the DEVSTAT2 register. The BUS_I_UV_ERR bit will be cleared once the supply returns above the threshold and either one Periodic Data Collection Mode status is transmitted with the VBUF_ERR bit set, or a response to a Command and Response Mode Register Read of the DEVSTAT2 register is transmitted. — If BUS_I falls below the specified threshold during a command transmission in Command and Response Mode, the command is ignored, and no DSI3 response transmission occurs. Once the supply returns above the threshold, the device will resume decoding commands. — If BUS_I falls below the specified threshold during a response transmission in Command and Response Mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume decoding commands. — If BUS_I falls below the specified threshold during a command transmission in Periodic Data Collection Mode, the command is ignored and no periodic response occurs during that period. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands. The device will resume decoding Background Diagnostic Mode commands after the Start Condition is met. — If BUS_I falls below the specified threshold during a periodic response transmission in Periodic Data Collection Mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands. The device will resume decoding Background Diagnostic Mode commands after the Start Condition is met. — If BUS_I falls below the specified threshold during a Background Diagnostic Mode response transmission in Periodic Data Collection Mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume periodic transmissions in response to commands. The device will resume decoding Background Diagnostic Mode commands after the Start Condition is met. • VBUF — If VBUF falls below the specified threshold at any time, the VBUF_UV_ERR bit is set in the DEVSTAT2 register. If a response transmission is in process, the response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold, the device will resume decoding commands and transmission of responses. The VBUF_UV_ERR bit will be cleared once the supply returns above the threshold and one Periodic Data Collection Mode status is transmitted with the VBUF_UV_ERR bit set. • VREG or VREGA — If VREG or VREGA falls below the specified threshold at any time, the device is reset. Reference Figure 7 for an example of a supply line interruption during a response in Periodic Data Collection Mode. Sensors 34 Freescale Semiconductor, Inc.
BUS_I V BUF V REG V REGA I DATA POR 3.3.3 V BUF Capacitance monitor Figure 7. BUS_I Microcut response A monitor circuit is incorporated to ensure predictable operation if the connection to the external V BUF capacitor becomes open. The V BUF regulator is disabled t POR_CAPTEST seconds after POR for a duration of t VBUFCAPTST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the threshold specified in Section 2.3 causing the VBUF_ERR bit to be set in the DEVSTAT2 register. Cap_Test V BUF V PORVBUF_f POR BUS_I microcut occurs BUS_I undervoltage detected Response Terminated t POR_CAPTEST t CAPTST_TIME Time Figure 8. V BUF Capacitor monitor MMA27XXW Sensors Freescale Semiconductor, Inc. 35 Time Capacitor Present Next Power on Cycle t POR_CAPTEST t CAPTST_TIME Capacitor Open
Page 1 and 2: Freescale Semiconductor Document Nu
Page 3 and 4: 1 Block Diagram, Pin Descriptions,
Page 5 and 6: 1.3 Application diagram C2 C3 C4 Ta
Page 7 and 8: 2 Electrical Characteristics 2.1 Ma
Page 9 and 10: 2.4 Electrical Characteristics - se
Page 11 and 12: 2.6 Dynamic electrical characterist
Page 13 and 14: 2.8 Dynamic electrical characterist
Page 15 and 16: 3.1.1 IC Type register The IC Type
Page 17 and 18: 3.1.9 Device Serial Number register
Page 19 and 20: 3.1.13.3 Clock Calibration Enable (
Page 21 and 22: 3.1.15.4 Periodic Data Collection M
Page 23 and 24: 3.1.19.2 Oscillator Training Error
Page 25 and 26: 3.1.19.14 BUS IN Undervoltage Error
Page 27 and 28: 3.1.22 DSI3 Communication CRC Polyn
Page 29 and 30: 3.1.25.1 Low-pass filter selection
Page 31 and 32: 3.1.28 Reserved Registers A registe
Page 33: 3.3 Voltage regulators The device d
Page 37 and 38: 3.4 Internal oscillator The device
Page 39 and 40: 3.5.2 Self-test interface The self-
Page 41 and 42: 3.5.4.1 Decimation Sinc filter The
Page 43 and 44: Figure 17. Low-pass filter characte
Page 49 and 50: 3.5.4.4 Signal compensation The dev
Page 51 and 52: Figure 24. 10 Hz offset cancellatio
Page 53 and 54: Figure 26. 0.1 Hz offset cancellati
Page 55 and 56: 3.6 DSI3 physical layer 3.6.1 Comma
Page 57 and 58: 3.6.2 Response transmitter The resp
Page 59 and 60: 3.7.2 Synchronous Sampling mode wit
Page 61 and 62: 4 DSI3 Protocol The DSI3 standard d
Page 63 and 64: 4.2.1.1 Bit encoding Figure 41 show
Page 65 and 66: 4.2.2.1 Symbol Encoding The device
Page 67 and 68: 4.2.3 DSI3 Command and Response Mod
Page 69 and 70: 4.2.4.2 Register Write Command The
Page 71 and 72: 4.2.4.4 Enter Periodic Data Collect
Page 73 and 74: 4.3.2 DSI3 Periodic Data Collection
Page 75 and 76: 4.3.3 DSI3 Periodic Data Collection
Page 77 and 78: 4.4 Maximum number of devices on a
Page 79 and 80: 6 Recommended Footprint Reference F
Page 81 and 82: CASE 2086-01 ISSUE C 16 LEAD QFN MM
Page 83 and 84: 8 Revision History Table 69. Revisi

Data Sheet - Freescale Semiconductor

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