Microcomputer Circuits and Processes

RD
WR
in/
out
8·bit address
row/column
select
256 cells
memory
data in/out
(one bit)
iigure 2.10
~epresentation of 256-bit memory as it
lay appear in a manufacturer's
>atabook. Note address lines, data line,
nd read (RD) and write (WR) lines.
To perform reads and writes, the in-out circuits must receive some
control signals, defining READ or WRITE. These come from the CPU
and are put on to the wires labelled RD (read) and WR (write). The
READ and WRITE signals form part of the control bus signals.
The whole memory chip is complete, and is shown again in figure
2.10. Note how the two 4-bit address numbers have been written as a
single 8-bit address. This memory chip will be able to store 256 different
numbers, but each number may be only 0 or 1. As before, to be able to
store numbers and letters we would like to store 8 bits at a time. To do
this we need 8 of these memory chips, as shown in figure 2.11. Each chip
is responsible for storing one bit of an 8-bit word. For example, if we
wanted to store the word 01011011, then the first chip would hold 0, the
second 1, the third 0, and so on. If all the address lines of the chips are
bussed in parallel, then each chip will store its own bit of the 8-bit word
at the same address. That makes life easy. To store an 8-bit number in
memory, you first give an 8-bit address (which each memory chip splits
into two 4-bit row--eolumn selects) and then send the 8-bit data word
whose bits each go to a memory chip.
8·bit address
bus
read/write
control
RD
WR
8 data wires
form
8-bit data bus
Figure 2.11
Joining 8 of the 256-bit memory chips to make a 256-byte memory boar~. Note how the
data bus is born.
We have rediscovered the bus. The address wires can be taken to the
CPU as an address bus and the data wires as a data bus. If you look
back at the bus mentioned in figure 2.5, which we called an 'information'
bus, you will now understand that it is really an address bus plus
a data bus. Before we increase the size of the memory one step further,
look again at figure 2.11. Note that the read (RD) and write (WR) wires
are all connected to common, respective, RD and WR lines. That is
because we want all the chips to respond simultaneously to a read or a
write operation. The whole 256-byte memory package can be redrawn.
In figure 2.12 it is shown connect~d to the address bus and, via a tristate
buffer, to the data bus of the computer system. Actually, manufacturers
put the tristate buffer in the data lines on to the chip to make life easy
for constructors. At this point, make sure you understand why there are
no buffers needed on the address lines for the memory joining the
address bus.
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