Microcomputer Circuits and Processes

says that this voltage, 0001, is smaller than 0011, Vin. So the comparator
outputs a logical 1 which is latched into the SAR. The SAR holds 0011,
bits 3, 2, and 1 being latched at 0, 0, and 1 respectively.
4 Finally, the SAR makes bit 0 go low, outputting 0010, bits 1 to 3
remaining latched. The D-to-A converts, and now the comparator sees
two equal voltages and outputs a logical 0 which is latched into the
SAR (note that the comparator is biased).
comparator
digital-to-analogue
data
bus
\.,..----------, i
SAR
control
enable
Jl..Jl...n..
start
clock conversion
Figure 4.29
Components of a successive approximation converter. The successive approximation
register (SAR) drives the D-to-A converter, which passes on the equivalent voltage to the
comparator. This compares the approximation voltage with JIIn> the input voltage. The
outcome of this comparison tells the SAR what to do next.
The conversion is done, and the SAR's output, 0010, can be enabled on
to the data bus and read into memory. Commercial SARs have a
'conversion done' signal to tell the CPU it may transfer the digital
information. Figure 4.30 shows the comparator's input for the above
four stages of conversion and the logic signal sent back to the SAR with
its meaning.
Note also that the output of the comparator is 0, then 0, then 1, then
0, as the conversion proceeds. This is the correct binary value for Vi",
comparator
1 r> 1
D-to-A input control
output voltage to SAR
1 0111 0010 0 too high
2 0011 0010 0 too high
3 0001 0010 1 too low
4 0010 0010 0 just right - both voltages
equal
Figure 4.30
The input to and output of the comparator for the four steps of successive approximation.
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