Microcomputer Circuits and Processes

A glance at the timing diagram in figure 2.28 will confirm that this
will work. The whole diagram refers to an output cycle, so M/IO is low,
and no memory is involved. The data bits to be sent to the television
screen appear on the address-data bus late on in the cycle, at the same
time as WR goes high.
clock
=x"'"-- a_d_d_re_ss >c address bus
=x address X data to TV screen >c. address-data bus
JI'---
RD
L-- WR high means
_
ALE
output
--, I MjTO low, i.e. input-output
1-1 ----', operation
Figure 2.28
Addition of the MilO signal to the timing diagram. Here, the MilO signal is low,
implying an input-output instruction. Also, the WR signal is high, implying a write, here
an output instruction.
M/ra RD WR
type of
operation
0 0
,
output
0 1 0 input
0
,
memory write
, , 0 memory read
Figure 2.29
Operation types for the allowed
combinations ofRD, WR, and MilO.
You can work out how input instructions are carried out using the
read (RD) line to open the buffer on the input device. The table in figure
2.29 summarizes the states of RD, WR, and M/IO for all types of CPU
operation, memory and in-out.
Although thiJ method of using M/IO will give one input and one
output device, rather more power than that is required. The 8086
processor can control 64000 input/output devices! The M/IO line gives
us that potential. Glance again at the timing in figure 2.28. Note that
there is an address on the address bus during the entire operation. Why
is this address not decoded and used to select an input-output device,
just as it was used earlier to select a memory card? That is in fact how it
works. When the CPU executes an OUT or IN instruction, it will send
an address which the programmer can write into the program, thus
selecting the input-output device. This select pulse is combined with
M/IO and RD or WR to enable the device's buffer. The hook-up is
shown in figure 2.30.
One input and one output device are shown. As before, the output
device is enabled by ANDing WR and M/IO inverted, but now it is also
ANDed with the device select signal coming from the 4-bit, 1-of-16
decoder. The input device is enabled by ANDing RD with M/IO
inverted and the device selection pulse. Other input-output devices
would use other selection signals, ANDing with RD, WR, and M/IO
inverted in the same way. With full decoding of an 8-bit address bus, the
system could control 2 8 = 256 input and 256 output devices. Already
our simple computer has enormous power.
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