User Manual - Terasic

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Chapter 3Using the DE0-Nano BoardThis chapter gives instructions for using the DE0-Nano board and describes in detail its componentsand connectors, along with the required pin assignments.3.1 Configuring the Cyclone IV FPGAThe DE0-Nano board contains a Cyclone IV E FPGA which can be programmed using JTAGprogramming. This allows users to configure the FPGA with a specified design using Quartus IIsoftware. The programmed design will remain functional on the FPGA as long as the board ispowered on, or until the device is reprogrammed. The configuration information will be lost whenthe power is turned off.To download a configuration bit stream file using JTAG Programming into the Cyclone IV FPGA,perform the following steps:1. Connect a USB Mini-B cable between a host computer and the DE0-Nano.2. The FPGA can now be programmed through the Quartus II Programmer by selecting aconfiguration bit stream file with the .sof filename extension.• Configuring the Spansion EPCS64 deviceThe DE0-Nano board contains a Spansion EPCS64 serial configuration device. This deviceprovides non-volatile storage of the configuration bit-stream, so that the information is retainedeven when the power supply to the DE0-Nano board is turned off. When the board’s power isturned on, the configuration data in the EPCS64 device is automatically loaded into the Cyclone IVE FPGA.The Cyclone IV E device supports in-system programming of a serial configuration device usingthe JTAG interface via the serial flash loader design. The serial flash loader is a bridge design forthe Cyclone IV E device that uses its JTAG interface to access the EPCS .jic file and then uses theAS interface to program the EPCS device. Figure 3-1 illustrates the programming method whenadopting a serial flash loader solution. Chapter 9 of this document describes how to load a circuit tothe serial configuration device.10
Figure 3-1 Programming a serial configuration device with serial flash loader solution• JTAG Chain on DE0-Nano BoardThe JTAG Chain on the DE0-Nano board is connected to a host computer using an on-boardUSB-blaster. The USB-blaster consists of a USB Mini-B connector, a FTDI USB 2.0 Controller,and an Altera MAX II CPLD.Figure 3-2 illustrates the JTAG configuration setup.Figure 3-2 JTAG Chain3.2 General <strong>User</strong> Input/Output• PushbuttonsThe DE0-Nano board contains two pushbuttons shown in Figure 3-3. Each pushbutton isdebounced using a Schmitt Trigger circuit, as indicated in Figure 3-4. The two outputs called KEY0,and KEY1 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA. Eachpushbutton provides a high logic level when it is not pressed, and provides a low logic level whenpressed. Since the pushbuttons are debounced, they are appropriate for using as clock or resetinputs.11
Page 4 and 5: Chapter 1IntroductionThe DE0-Nano b
Page 6: 1.2 About the KITThe kit comes with
Page 9: 2.3 Power-up the DE0-Nano BoardThe
Page 16 and 17: Figure 3-7 Connections between FPGA
Page 18 and 19: GPIO_03 PIN_A3 GPIO Connection DATA
Page 20 and 21: Figure 3-10 Pin distribution of the
Page 22 and 23: 3.7 Digital AccelerometerThe ADXL34
Page 24 and 25: • Power Distribution SystemFigure
Page 26 and 27: 8. The Control Panel is now ready f
Page 28 and 29: 4.3 Switches and PushbuttonsChoosin
Page 30 and 31: The Sequential Read function is use
Page 32 and 33: 4.7 Overall Structure of the DE0-Na
Page 34 and 35: The generated system is described u
Page 36 and 37: Figure 5-3 The DE0-Nano Board Type
Page 38 and 39: Figure 5-6 Project Settings• Proj
Page 40 and 41: 6.2 Before You BeginThis tutorial a
Page 42 and 43: The driver is available within the
Page 44 and 45: The driver will now be installed as
Page 46 and 47: Figure 6-9 Project informationd. Cl
Page 48: Figure 6-11 my_first_fpga project6.
Page 52 and 53: always @ (posedge CLOCK_5)// on pos
Page 54 and 55: 14. Press the Esc key or click an e
Page 56 and 57: d. Click Next.Figure 6-21 MegaWizar
Page 58 and 59: Figure 6-23 MegaWizard Plug-In Mana
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Figure 6-25 PLL Symbol11. Click OK
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4. Place the new pin onto the BDF s
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Figure 6-31 Change the output BUS n
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Figure 6-34 lpm_mux settings9. Clic
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15. Add input buses and output pins
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Figure 6-40 Adding the KEY [0] Inpu
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Figure 6-42 Completed Pin Planning
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Figure 6-44 Compilation Message for
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Figure 6-46 Programmer Window2. Cli
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Figure 6-48 Downloading CompleteCon
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Figure 6-50 Setting unused pinsClic
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Figure 7-1 Start to Create a New Pr
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Figure 7-5 New Project Wizard: Fami
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Figure 7-8 A New Complete Project5.
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Figure 7-12 Create New System[2]7.
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Figure 7-15 Nios II Processor9. Cli
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Figure 7-17 Rename the CPU (1)Figur
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Figure 7-20 JTAG UART’s add wizar
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Figure 7-22 Rename JTAG UART15. Add
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Figure 7-24 On-Chip Memory Box16. M
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Figure 7-26 Add On-Chip memory17. R
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Figure 7-29 Updated CPU settings19.
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Figure 7-31 Add PIO20. Click Finish
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22. Select System > Auto-Assign Bas
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Figure 7-38 SOPC Builder generation
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33. Figure 7-42 show a blank Verilo
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Figure 7-43 Input verilog TextFigur
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36. Compile the project, by selecti
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Figure 7-51 Blank Pins39. Input Loc
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Figure 7-54 Quartus II ProgrammerTh
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Figure 7-55 Nios II IDE New Project
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● alt_sys_init.c: an initializati
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#include "system.h"#include "altera
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can write to the PIO data register,
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Figure 7-61 Configuring System Libr
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Figure 8-2 Pulse Width ModulationFi
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Table 8-1 DIP Switch SettingsDIP Sw
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Figure 8-5 ADC Reading hardware set
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• KEYThe KEY button is driven by
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Figure 8-11 4-wire SPI Timing Diagr
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• Input “1” to start Analog t
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In this demo, the accelerometer is
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Figure 9-1 Convert Programming File
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Figure 9-3 Select Devices Page146
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Figure 9-5 Compression the sof file
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Figure 9-7 Erasing setting in Quart
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User Manual - Terasic

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