User Manual - Terasic

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Chapter 1IntroductionThe DE0-Nano board introduces a compact-sized FPGA development platform suited for to a widerange of portable design projects, such as robots and mobile projects.The DE0-Nano is ideal for use with embedded soft processors—it features a powerful Altera CycloneIV FPGA (with 22,320 logic elements), 32 MB of SDRAM, 2 Kb EEPROM, and a 64 Mb serialconfiguration memory device. For connecting to real-world sensors the DE0-Nano includes aNational Semiconductor 8-channel 12-bit A/D converter, and it also features an Analog Devices13-bit, 3-axis accelerometer device.The DE0-Nano board includes a built-in USB Blaster for FPGA programming, and the board can bepowered either from this USB port or by an external power source. The board includes expansionheaders that can be used to attach various <strong>Terasic</strong> daughter cards or other devices, such as motorsand actuators. Inputs and outputs include 2 pushbuttons, 8 user LEDs and a set of 4 dip-switches.1.1 FeaturesFigure 1-1 shows a photograph of the DE0-Nano Board.Figure 1-1 The DE0-Nano Board4
The key features of the board are listed below:• Featured deviceo Altera Cyclone® IV EP4CE22F17C6N FPGAo 153 maximum FPGA I/O pins• Configuration status and set-up elementso On-board USB-Blaster circuit for programmingo Spansion EPCS64• Expansion headero Two 40-pin Headers (GPIOs) provide 72 I/O pins, 5V power pins, two 3.3V power pins andfour ground pins• Memory deviceso 32MB SDRAMo 2Kb I2C EEPROM• General user input/outputo 8 green LEDso 2 debounced pushbuttonso 4-position DIP switch• G-Sensoro ADI ADXL345, 3-axis accelerometer with high resolution (13-bit)• A/D Convertero NS ADC128S022, 8-Channel, 12-bit A/D Convertero 50 Ksps to 200 Ksps• Clock systemo On-board 50MHz clock oscillator• Power Supplyo USB Type mini-AB port (5V)o DC 5V pin for each GPIO header (2 DC 5V pins)o 2-pin external power header (3.6-5.7V)5
Page 6: 1.2 About the KITThe kit comes with
Page 9 and 10: 2.3 Power-up the DE0-Nano BoardThe
Page 11: Figure 3-1 Programming a serial con
Page 16 and 17: Figure 3-7 Connections between FPGA
Page 18 and 19: GPIO_03 PIN_A3 GPIO Connection DATA
Page 20 and 21: Figure 3-10 Pin distribution of the
Page 22 and 23: 3.7 Digital AccelerometerThe ADXL34
Page 24 and 25: • Power Distribution SystemFigure
Page 26 and 27: 8. The Control Panel is now ready f
Page 28 and 29: 4.3 Switches and PushbuttonsChoosin
Page 30 and 31: The Sequential Read function is use
Page 32 and 33: 4.7 Overall Structure of the DE0-Na
Page 34 and 35: The generated system is described u
Page 36 and 37: Figure 5-3 The DE0-Nano Board Type
Page 38 and 39: Figure 5-6 Project Settings• Proj
Page 40 and 41: 6.2 Before You BeginThis tutorial a
Page 42 and 43: The driver is available within the
Page 44 and 45: The driver will now be installed as
Page 46 and 47: Figure 6-9 Project informationd. Cl
Page 48: Figure 6-11 my_first_fpga project6.
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always @ (posedge CLOCK_5)// on pos
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14. Press the Esc key or click an e
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d. Click Next.Figure 6-21 MegaWizar
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Figure 6-23 MegaWizard Plug-In Mana
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Figure 6-25 PLL Symbol11. Click OK
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4. Place the new pin onto the BDF s
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Figure 6-31 Change the output BUS n
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Figure 6-34 lpm_mux settings9. Clic
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15. Add input buses and output pins
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Figure 6-40 Adding the KEY [0] Inpu
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Figure 6-42 Completed Pin Planning
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Figure 6-44 Compilation Message for
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Figure 6-46 Programmer Window2. Cli
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Figure 6-48 Downloading CompleteCon
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Figure 6-50 Setting unused pinsClic
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Figure 7-1 Start to Create a New Pr
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Figure 7-5 New Project Wizard: Fami
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Figure 7-8 A New Complete Project5.
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Figure 7-12 Create New System[2]7.
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Figure 7-15 Nios II Processor9. Cli
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Figure 7-17 Rename the CPU (1)Figur
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Figure 7-20 JTAG UART’s add wizar
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Figure 7-22 Rename JTAG UART15. Add
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Figure 7-24 On-Chip Memory Box16. M
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Figure 7-26 Add On-Chip memory17. R
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Figure 7-29 Updated CPU settings19.
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Figure 7-31 Add PIO20. Click Finish
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22. Select System > Auto-Assign Bas
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Figure 7-38 SOPC Builder generation
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33. Figure 7-42 show a blank Verilo
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Figure 7-43 Input verilog TextFigur
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36. Compile the project, by selecti
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Figure 7-51 Blank Pins39. Input Loc
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Figure 7-54 Quartus II ProgrammerTh
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Figure 7-55 Nios II IDE New Project
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● alt_sys_init.c: an initializati
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#include "system.h"#include "altera
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can write to the PIO data register,
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Figure 7-61 Configuring System Libr
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Figure 8-2 Pulse Width ModulationFi
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Table 8-1 DIP Switch SettingsDIP Sw
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Figure 8-5 ADC Reading hardware set
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• KEYThe KEY button is driven by
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Figure 8-11 4-wire SPI Timing Diagr
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• Input “1” to start Analog t
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In this demo, the accelerometer is
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Figure 9-1 Convert Programming File
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Figure 9-3 Select Devices Page146
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Figure 9-5 Compression the sof file
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Figure 9-7 Erasing setting in Quart
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User Manual - Terasic

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