User Manual - Terasic

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• Power Distribution SystemFigure 3-16 shows the power distribution system on the DE0-Nano board.Figure 3-16 DE0-Nano Power Distribution System24
Chapter 4DE0-Nano Control PanelThe DE0-Nano board comes with a Control Panel facility that allows users to access variouscomponents on the board from a host computer. The host computer communicates with the boardthrough a USB connection. The facility can be used to verify the functionality of components on theboard or be used as a debug tool while developing RTL code.This chapter first presents some basic functions of the Control Panel, then describes its structure inblock diagram form, and finally describes its capabilities.4.1 Control Panel SetupThe Control Panel Software Utility is located in the directory “tools/DE0_NANO_ControlPanel” inthe DE0-Nano System CD. It's free of installation, just copy the whole folder to your host computerand launch the control panel by executing the “DE0_NANO_ControlPanel.exe”.When Control Panel starts it will attempt to download a configuration file onto the DE0-Nano board.The configuration file contains a design that communicates with the peripheral devices on the boardthat are attached to the FPGA device. Perform the following steps to ensure that the control panelstarts up successfully:1. Make sure Quartus II 10.0 or later version is installed successfully on your PC.2. Connect a USB A to Mini-B cable to a USB (Type A) host port and to the board.3. Start the executable DE0_NANO_ControlPanel.exe on the host computer. The Control Paneluser interface shown in Figure 4-1 will appear.5. The DE0_NANO_ControlPanel.sof bit stream is loaded automatically as soon as theDE0_NANO_ControlPanel.exe is launched.6. In case the connection is disconnected, click on CONNECT where the .sof will be re-loadedonto the board.Note: the Control Panel will occupy the USB port until you choose to close the program ordisconnect it from the board by clicking the Disconnect button. While the Control Panel isconnected to the board, you will be unable to use Quartus II to download a configuration file intothe FPGA.25
Page 4 and 5: Chapter 1IntroductionThe DE0-Nano b
Page 6: 1.2 About the KITThe kit comes with
Page 9 and 10: 2.3 Power-up the DE0-Nano BoardThe
Page 11: Figure 3-1 Programming a serial con
Page 16 and 17: Figure 3-7 Connections between FPGA
Page 18 and 19: GPIO_03 PIN_A3 GPIO Connection DATA
Page 20 and 21: Figure 3-10 Pin distribution of the
Page 22 and 23: 3.7 Digital AccelerometerThe ADXL34
Page 26 and 27: 8. The Control Panel is now ready f
Page 28 and 29: 4.3 Switches and PushbuttonsChoosin
Page 30 and 31: The Sequential Read function is use
Page 32 and 33: 4.7 Overall Structure of the DE0-Na
Page 34 and 35: The generated system is described u
Page 36 and 37: Figure 5-3 The DE0-Nano Board Type
Page 38 and 39: Figure 5-6 Project Settings• Proj
Page 40 and 41: 6.2 Before You BeginThis tutorial a
Page 42 and 43: The driver is available within the
Page 44 and 45: The driver will now be installed as
Page 46 and 47: Figure 6-9 Project informationd. Cl
Page 48: Figure 6-11 my_first_fpga project6.
Page 52 and 53: always @ (posedge CLOCK_5)// on pos
Page 54 and 55: 14. Press the Esc key or click an e
Page 56 and 57: d. Click Next.Figure 6-21 MegaWizar
Page 58 and 59: Figure 6-23 MegaWizard Plug-In Mana
Page 60 and 61: Figure 6-25 PLL Symbol11. Click OK
Page 62 and 63: 4. Place the new pin onto the BDF s
Page 64 and 65: Figure 6-31 Change the output BUS n
Page 66 and 67: Figure 6-34 lpm_mux settings9. Clic
Page 68 and 69: 15. Add input buses and output pins
Page 70 and 71: Figure 6-40 Adding the KEY [0] Inpu
Page 72 and 73: Figure 6-42 Completed Pin Planning
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Figure 6-44 Compilation Message for
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Figure 6-46 Programmer Window2. Cli
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Figure 6-48 Downloading CompleteCon
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Figure 6-50 Setting unused pinsClic
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Figure 7-1 Start to Create a New Pr
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Figure 7-5 New Project Wizard: Fami
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Figure 7-8 A New Complete Project5.
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Figure 7-12 Create New System[2]7.
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Figure 7-15 Nios II Processor9. Cli
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Figure 7-17 Rename the CPU (1)Figur
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Figure 7-20 JTAG UART’s add wizar
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Figure 7-22 Rename JTAG UART15. Add
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Figure 7-24 On-Chip Memory Box16. M
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Figure 7-26 Add On-Chip memory17. R
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Figure 7-29 Updated CPU settings19.
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Figure 7-31 Add PIO20. Click Finish
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22. Select System > Auto-Assign Bas
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Figure 7-38 SOPC Builder generation
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33. Figure 7-42 show a blank Verilo
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Figure 7-43 Input verilog TextFigur
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36. Compile the project, by selecti
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Figure 7-51 Blank Pins39. Input Loc
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Figure 7-54 Quartus II ProgrammerTh
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Figure 7-55 Nios II IDE New Project
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● alt_sys_init.c: an initializati
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#include "system.h"#include "altera
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can write to the PIO data register,
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Figure 7-61 Configuring System Libr
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Figure 8-2 Pulse Width ModulationFi
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Table 8-1 DIP Switch SettingsDIP Sw
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Figure 8-5 ADC Reading hardware set
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• KEYThe KEY button is driven by
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Figure 8-11 4-wire SPI Timing Diagr
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• Input “1” to start Analog t
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In this demo, the accelerometer is
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Figure 9-1 Convert Programming File
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Figure 9-3 Select Devices Page146
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Figure 9-5 Compression the sof file
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Figure 9-7 Erasing setting in Quart
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User Manual - Terasic

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