User Manual - Terasic

Figure 6-43 Default SDCNaming the SDC with the same name as the top-level file causes the Quartus II software to use thistiming analysis file automatically by default. If you used another name, you would need to add theSDC to the Quartus II assignments file.6.8 Compile Your DesignAfter creating your design you must compile it. Compilation converts the design into a bitstreamthat can be downloaded into the FPGA. The most important output of compilation is an SRAMObject File (.sof), which you use to program the device. Also, the software generates report filesthat provide information about your circuit as it compiles.Now that you have created a complete Quartus II project and entered all assignments, you cancompile the design.In the Processing menu, select Start Compilation or click the Play button on the toolbar.If you are asked to save changes to your BDF, click Yes.While compiling your design, the Quartus II software provides useful information about thecompilation, as shown in Figure 6-44.73