User Manual - Terasic

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The driver will now be installed as indicated in Figure 6-7. Click Finish and you can start using theDE0-Nano board.Figure 6-7 The driver is installed6.3 What You Will LearnIn this tutorial you will perform the following tasks:Create a design that causes LEDs on the development board to blink at two distinct rates. Thisdesign is easy to create and gives you visual feedback that the design works. Of course, you can useyour DE0-Nano board to run other designs as well. For the LED design, you will write Verilog HDLcode for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as the clock source,and add a 2-input multiplexer megafunction. When the design is running on the board, you canpress an input switch to multiplex the counter bits that drive the output LEDs.6.4 Assign The DeviceBegin this tutorial by creating a new Quartus II project. A project is a set of files that maintaininformation about your FPGA design. The Quartus II Settings File (.qsf) and Quartus II Project File(.qpf) files are the primary files in a Quartus II project. To compile a design or make pinassignments, you must first create a project. The steps used to create a project are:44
1. In the Quartus II software, select File > New Project Wizard. The Introduction page opens, asshown in Figure 6-8.Figure 6-8 New Project Wizard introduction2. Click Next.3. Enter the following information about your project: (Note: File names, project names, anddirectories in the Quartus II software cannot contain spaces.)a. What is the working directory for this project? Enter a directory in which you will store yourQuartus II project files for this design. For example, E:\My_design\my_first_fpga.b. What is the name of this project? Type my_first_fpga.c. What is the name of the top-level design entity for this project? Type my_first_fpga. SeeFigure 6-9.45
Page 4 and 5: Chapter 1IntroductionThe DE0-Nano b
Page 6: 1.2 About the KITThe kit comes with
Page 9 and 10: 2.3 Power-up the DE0-Nano BoardThe
Page 11: Figure 3-1 Programming a serial con
Page 16 and 17: Figure 3-7 Connections between FPGA
Page 18 and 19: GPIO_03 PIN_A3 GPIO Connection DATA
Page 20 and 21: Figure 3-10 Pin distribution of the
Page 22 and 23: 3.7 Digital AccelerometerThe ADXL34
Page 24 and 25: • Power Distribution SystemFigure
Page 26 and 27: 8. The Control Panel is now ready f
Page 28 and 29: 4.3 Switches and PushbuttonsChoosin
Page 30 and 31: The Sequential Read function is use
Page 32 and 33: 4.7 Overall Structure of the DE0-Na
Page 34 and 35: The generated system is described u
Page 36 and 37: Figure 5-3 The DE0-Nano Board Type
Page 38 and 39: Figure 5-6 Project Settings• Proj
Page 40 and 41: 6.2 Before You BeginThis tutorial a
Page 42 and 43: The driver is available within the
Page 46 and 47: Figure 6-9 Project informationd. Cl
Page 48: Figure 6-11 my_first_fpga project6.
Page 52 and 53: always @ (posedge CLOCK_5)// on pos
Page 54 and 55: 14. Press the Esc key or click an e
Page 56 and 57: d. Click Next.Figure 6-21 MegaWizar
Page 58 and 59: Figure 6-23 MegaWizard Plug-In Mana
Page 60 and 61: Figure 6-25 PLL Symbol11. Click OK
Page 62 and 63: 4. Place the new pin onto the BDF s
Page 64 and 65: Figure 6-31 Change the output BUS n
Page 66 and 67: Figure 6-34 lpm_mux settings9. Clic
Page 68 and 69: 15. Add input buses and output pins
Page 70 and 71: Figure 6-40 Adding the KEY [0] Inpu
Page 72 and 73: Figure 6-42 Completed Pin Planning
Page 74 and 75: Figure 6-44 Compilation Message for
Page 76 and 77: Figure 6-46 Programmer Window2. Cli
Page 78 and 79: Figure 6-48 Downloading CompleteCon
Page 80 and 81: Figure 6-50 Setting unused pinsClic
Page 82 and 83: Figure 7-1 Start to Create a New Pr
Page 84 and 85: Figure 7-5 New Project Wizard: Fami
Page 86 and 87: Figure 7-8 A New Complete Project5.
Page 88 and 89: Figure 7-12 Create New System[2]7.
Page 90 and 91: Figure 7-15 Nios II Processor9. Cli
Page 92 and 93: Figure 7-17 Rename the CPU (1)Figur
Page 94 and 95:
Figure 7-20 JTAG UART’s add wizar
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Figure 7-22 Rename JTAG UART15. Add
Page 98 and 99:
Figure 7-24 On-Chip Memory Box16. M
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Figure 7-26 Add On-Chip memory17. R
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Figure 7-29 Updated CPU settings19.
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Figure 7-31 Add PIO20. Click Finish
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22. Select System > Auto-Assign Bas
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Figure 7-38 SOPC Builder generation
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33. Figure 7-42 show a blank Verilo
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Figure 7-43 Input verilog TextFigur
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36. Compile the project, by selecti
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Figure 7-51 Blank Pins39. Input Loc
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Figure 7-54 Quartus II ProgrammerTh
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Figure 7-55 Nios II IDE New Project
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● alt_sys_init.c: an initializati
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#include "system.h"#include "altera
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can write to the PIO data register,
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Figure 7-61 Configuring System Libr
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Figure 8-2 Pulse Width ModulationFi
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Table 8-1 DIP Switch SettingsDIP Sw
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Figure 8-5 ADC Reading hardware set
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• KEYThe KEY button is driven by
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Figure 8-11 4-wire SPI Timing Diagr
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• Input “1” to start Analog t
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In this demo, the accelerometer is
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Figure 9-1 Convert Programming File
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Figure 9-3 Select Devices Page146
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Figure 9-5 Compression the sof file
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Figure 9-7 Erasing setting in Quart
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